21
M37905M4C-XXXFP, M37905M4C-XXXSP
M37905M6C-XXXFP, M37905M6C-XXXSP
M37905M8C-XXXFP, M37905M8C-XXXSP
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
INTERRUPTS
Table 3 shows the interrupt sources and the corresponding interrupt
vector addresses. Reset is also handled as an interrupt source in
this section, too.
DBC and BRK instruction are interrupts used only for debugging.
Therefore, do not use these interrupts.
Interrupts other than reset, watchdog timer, zero divide, and address
matching detection all have interrupt control registers. Table 4 shows
the addresses of the interrupt control registers and Figure 13 shows
the bit configuration of the interrupt control register.
The interrupt request bit is automatically cleared by the hardware
during reset or when processing an interrupt. Also, interrupt request
bits except for that of a watchdog timer interrupt can be cleared by
software.
An INT
i
(i = 0 to 7) interrupt request is generated by an external in-
put.
INT
i
is an external interrupt; whether to cause an interrupt at the in-
put level (level sense) or at the edge (edge sense) can be selected
with the level/edge select bit. Furthermore, the polarity of the inter-
rupt input can be selected with the polarity select bit.
When using the following pins as external interrupt input pins, be
sure to clear the direction registers of the corresponding multiplexed
ports to “0”: pins P5
1
/INT
1
, P5
2
/INT
2
, P5
3
/INT
3
, P5
5
/INT
5
, P5
6
/INT
6
,
and P5
7
/INT
7
.
When the external interrupt input read register (address 95
16
), which
is shown in Figure 12, is read out, the status of pins INT
0
through
INT
7
can directly be read.
Timer and UART interrupts are described in the respective section.
The priority of interrupts when multiple interrupt requests are caused
simultaneously is partially fixed by hardware, but, it can also be ad-
justed by software as shown in Figure 14.
The hardware priority is fixed as the following:
reset > watchdog timer > other interrupts
Interrupts
UART2 transmit
UART2 receive
Timer A9
Timer A8
Timer A7
Timer A6
Timer A5
INT
7
external interrupt
INT
6
external interrupt
INT
5
external interrupt
Address matching detection interrupt
INT
4
external interrupt
INT
3
external interrupt
A-D conversion
UART1 transmit
UART1 receive
UART0 transmit
UART0 receive
Timer B2
Timer B1
Timer B0
Timer A4
Timer A3
Timer A2
Timer A1
Timer A0
INT
2
external interrupt
INT
1
external interrupt
INT
0
external interrupt
Watchdog timer
DBC (Do not select.)
Break instruction (Do not select.)
Zero divide
Reset
Table 3. Interrupt sources and interrupt vector addresses
Vector addresses
00FFB4
16
00FFB5
16
00FFB6
16
00FFB7
16
00FFB8
16
00FFB9
16
00FFBA
16
00FFBB
16
00FFBC
16
00FFBE
16
00FFC0
16
00FFC2
16
00FFC4
16
00FFC6
16
00FFCA
16
00FFCB
16
00FFD0
16
00FFD1
16
00FFD2
16
00FFD3
16
00FFD4
16
00FFD6
16
00FFD8
16
00FFDA
16
00FFDC
16
00FFDE
16
00FFE0
16
00FFE2
16
00FFE4
16
00FFE6
16
00FFE8
16
00FFEA
16
00FFEC
16
00FFEE
16
00FFF0
16
00FFF2
16
00FFF6
16
00FFF8
16
00FFFA
16
00FFFC
16
00FFFE
16
00FFBD
16
00FFBF
16
00FFC1
16
00FFC3
16
00FFC5
16
00FFC7
16
00FFD5
16
00FFD7
16
00FFD9
16
00FFDB
16
00FFDD
16
00FFDF
16
00FFE1
16
00FFE3
16
00FFE5
16
00FFE7
16
00FFE9
16
00FFEB
16
00FFED
16
00FFEF
16
00FFF1
16
00FFF3
16
00FFF7
16
00FFF9
16
00FFFB
16
00FFFD
16
00FFFF
16
Fig. 12 Bit configuration of external interrupt input read register
7
6
5
4
3
2
1
0
INT
0
read bit
INT
1
read bit
INT
2
read bit
INT
3
read bit
INT
4
read bit
INT
5
read bit
INT
6
read bit
INT
7
read bit
External interrupt input read register
Address
95
16