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57
M37905M4C-XXXFP, M37905M4C-XXXSP
M37905M6C-XXXFP, M37905M6C-XXXSP
M37905M8C-XXXFP, M37905M8C-XXXSP
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
CLOCK SYNCHRONOUS SERIAL COMMUNI-
CATION
A case where communication is performed between two clock syn-
chronous serial I/O ports as shown in Figure 65 will be described.
(The transmission side will be denoted by subscript j and the receiv-
ing side will be denoted by subscript k.)
Bit 0 of the UARTj transmit/receive mode register and UARTk trans-
mit/receive mode register must be set to “1” and bits 1 and 2 must be
“0”. The length of the transmission data is fixed at 8 bits.
Bit 3 of the UARTj transmit/receive mode register of the clock send-
ing side is cleared to “0” to select the internal clock. Bit 3 of the
UARTk transmit/receive mode register of the clock receiving side is
set to “1” to select the external clock. Bits 4, 5 and 6 are ignored in
clock synchronous mode. Bit 7 must always be “0”.
The clock source is selected by bit 0 (CS
0
) and bit 1 (CS
1
) of the
clock-sending-side UARTj transmit/receive control register 0. As
shown in Figure 60, the selected clock is divided by (n + 1), then by
2, is passed through a transmission control circuit, and is output as
transmission clock CLK
j
. Therefore, when the selected clock is fi,
Bit Rate = f
i
/ {(n + 1)
×
2}
On the clock receiving side, the CS
0
and CS
1
bits of the UARTk
transmit/receive control register 0 are ignored because an external
clock is selected.
Both of UART0 and UART1 can use CTS and RTS functions.
Bit 4 of the UARTi transmit/receive control register 0 is used to de-
termine whether to use CTS or RTS signal. Bit 4 must be “0” when
CTS or RTS signal is used. Bit 4 must be “1” when CTS and RTS sig-
nals are not used. When CTS and RTS signals are not used, CTS/
RTS pin can be used as a normal port pin.
When using pin CTS/RTS, :
If bit 2 of the UARTi transmit/receive control register 0 is cleared to
“0”, CTS input is selected.
If bit 2 is set to “1”, RTS output is selected.
The case using CTS and RTS signals are explained below. As
shown in Figure 72, bits 2, 3 and 5 of the serial I/O pin control regis-
ter can determine whether port pins P1
3,
P1
7
and P8
3
are used as
pins T
x
D
i
or as port pins. When bits 2, 3 and 5 are “0”, P1
3,
P1
7
and
P8
3
function as pins T
x
D
i
; when bits 2, 3 and 5 are “1”, P1
3,
P1
7
and
P8
3
function as port pins. Therefore, in the input-only system where
pins T
x
D
i
are not used, pins T
x
D
i
can function as port pins.
Fig. 65 Clock synchronous serial communication
UARTj transmit register
T
x
D
j
R
x
D
j
CLK
j
CTS
j
UARTj transmit buffer register
UARTj receive buffer register
UARTj receive register
UARTj Transmit/Receive mode register
UARTj Transmit/Receive control
register 0
UARTj Transmit/Receive control
register 1
0
0
0
0
T
X
EPTY
CS
1
CS
0
RE
RI
OER
FER
PER
CPL
CPL
SUM
TI
TE
0
UARTk transmit register
UARTk transmit buffer register
UARTk receive buffer register
UARTk receive register
UARTk Transmit/Receive mode register
UARTk Transmit/Receive control
register 0
UARTk Transmit/Receive control
register 1
0
1
1
0
1
T
X
EPTY
MSB
/LSB
RE
RI
OER
FER
PER
SUM
TI
TE
0
1
T
x
D
k
R
x
D
k
CLK
k
RTS
k
MSB
/LSB