PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
M37736MHBXXXGP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
38
ASYNCHRONOUS SERIAL COMMUNICATION
(UART)
Asynchronous serial communication can be performed using 7-, 8-,
or 9-bit length data. The operation is the same for all data lengths.
The following is the description for 8-bit asynchronous communication.
With 8-bit asynchronous communication, the bits 2 to 0 of the UART
i
transmit/receive mode register must be “101”.
Bit 3 is used to select an internal clock or an external clock. When bit
3 is “0”, an internal clock is selected and when bit 3 is “1”, then external
clock is selected. When an internal clock is selected, the bit 0 (CS
0
)
and bit 1 (CS
1
) of UART
i
transmit/receive control register 0 are used
to select the clock source. When an internal clock is selected for
asynchronous serial communication, the CLK
i
pin can be used as a
normal port.
When the content of the bit rate generator is n, the selected internal
or external clock is divided by (n + 1), then by 16, and passed through
a control circuit to create the UART transmission clock or the UART
receive clock.
When the selected clock is an internal clock fi or an external clock
f
EXT
,
Bit Rate = (fi or f
EXT
) / {(n + 1)
16}
Bit 4 selects 1 stop bit or 2 stop bits.
The bit 5 is a selection bit of odd parity or even parity.
In the odd parity mode, the parity bit is adjusted so that the sum of
the 1’s in the data and parity bit is always odd.
In the even parity mode, the parity bit is adjusted so that the sum of
the 1’s in the data and parity bit is always even.
Fig. 47 Transmit timing example when 9-bit asynchronous communication with no parity and 2 stop bits is selected
Fig. 46 Transmit timing example when 8-bit asynchronous communication with parity and 1 stop bit is selected
D
6
D
7
ST
D
1
D
2
D
3
D
4
D
5
P SP ST
STD
0
D
1
TE
i
(1 / f
1
, or 1 / f
EXT
)
(n + 1)
16
Transmission clock
CTS
i
Write in transmission buffer register
TI
i
T
ENDi
T
X
D
i
T
X
EPTY
i
Transmission register
←
Transmission
buffer register
Stopped because TEi = “0”
Start bit
Parity bit Stop bit
D
0
D
6
D
7
D
1
D
2
D
3
D
4
D
5
P
SP
D
0
TE
i
Transmission clock
TI
i
T
ENDi
T
X
D
i
T
X
EPTY
i
(1 / f
1
, or 1 / f
EXT
)
(n + 1)
16
Write in transmission buffer register
Transmission register
←
Transmission
buffer register
Stopped because
TEi = “0”
ST D
0
D
1
Start bit
Stop Bit Stop Bit
D
6
ST
D
1
D
2
D
3
D
4
D
5
D
8
SP
D
0
D
6
D
7
D
1
D
2
D
3
D
4
D
5
SP
D
0
D
7
SP
SP
D
8
ST
D
2