參數(shù)資料
型號: M37736EHL
廠商: Mitsubishi Electric Corporation
英文描述: PROM VERSION OF M37736MHLXXXHP(MICROCOMPUTERS)
中文描述: PROM的版本M37736MHLXXXHP(微型)
文件頁數(shù): 35/96頁
文件大?。?/td> 1328K
代理商: M37736EHL
35
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
M37736MHBXXXGP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
The internal/external clock polarity is selected with bit 6 (CPL) of the
UART
j
transmit/receive control register 0. When bit 6 is “0”, transmit
data is output at the CLK
j
’s falling edge in transmitting, received data
is input at the CLK
k
’s rising edge in receiving, and the CLK
i
level is
“H” not in transferring (transmitting/receiving). When bit 6 is “1”,
reversely, transmit data is output at the CLK
j
’s rising edge in
transmitting, received data is input at the CLK
k
’s falling edge in
receiving, and the CLK
i
level is “L” not in transferring. Bit transfer
order of transmit/received data, which is LSB first or MSB first (Note),
is selected with bit 7 (TFM) of the UART
j
transmit/receive control
register 0. LSB first is selected when bit 7 is “0”, and MSB first is
selected when bit 7 is “1”. However, UART2’s function is fixed to the
function specified by TxS=CPL=TFM=“0”, and it cannot be changed.
Note that, only in the UART
0
transmission mode, the transmission
clock can be output not only from the CLK
0
pin but also from the
other output pins (CLKS
0
, CLKS
1
). Transmission clock output multiple-
selection mode is set with the serial transmit control register and
others. For details, refer to the section on transmission.
Note.
When LSB first is selected, data is transmitted/received
beginning at the least significant bit (LSB). When MSB first is
selected, data is transmitted/received beginning at the most
significant bit (MSB).
Transmission
Transmission is started when the bit 0 (TE
j
flag) of the UART
j
transmit/
j
flag) of one is “0”, and the
___
CTS
j
input is “L”.
Transmit data is output each time when the transmission clock (CLK
j
)
level changes from “H” to “L” with bit 6 (CPL) of the UART
j
transmit/
receive control register 0 “0” or is output each time when the CLK
j
level changes from “L” to “H” with CPL “1”. For details, refer to Figure
42. In addition, transmit data is output beginning at the least significant
bit (LSB) with bit 7 (TFM) of the UART
j
transmit/receive control register
“0” or is output beginning at the most significant bit (MSB) with TFM
“1”.
The TI
j
flag indicates whether the transmission buffer register is empty
or not. It is cleared to “0” when date is written in the transmission
buffer register and set to “1” when the contents of the transmission
buffer register is transferred to the transmission register.
Fig. 42 Clock synchronous serial I/O timing
TE
j
Transmission
clock
(CPL =
“0” )
T
ENDj
CTSj
1 / f
i
( n + 1 )
2
Write in transmission buffter register
D
0
D
1
D
2
D
3
D
4
D
5
TI
j
(CPL =
“1” )
CLK
j
(TFM =
“0” )
(TFM =
“1” )
T
X
D
j
T
X
EPTY
j
1 / f
i
( n + 1 )
2
Stopped because TE
j
= “0”
D
6
D
7
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
Transmission register
Transmission buffter register
相關(guān)PDF資料
PDF描述
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M37736EHBXXXGP PROM VERSION OF M37736MHBXXXGP(MICROCOMPUTERS)
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