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APPLICAT ION
7721 Group User’s Manual
16–4
16.1 Memory connection
16.1.2 How to calculate timing
Timings at which data is read or written when connecting a memory and precautions when connecting a
memory are described below.
For timing requirements of the memory and detailed account except limits described below, also refer to
the memory’s Data book etc. When using bus buffers, various logical circuits, etc., be sure to consider the
propagation delay time etc.
(1)
Timing for reading data
When reading data, the external data bus is placed in a floating state, and data is read from the
external memory. This floating state is maintained after the falling edge of the E signal until an
interval of t
pzx(E–DLZ/DHZ)
has passed after the rising edge of the E signal. Satisfy t
su(DL/DH-E)
when inputting
data read from the external memory.
The following are described below:
Timing for reading data from the flash memory, SRAM, and DRAM
Calculation formulas for the external memory’s access time, which are for t
su(DL/DH-E)
to be satisfied
The memory output enable signal (OE) is assumed to be generated from the E signal.
G
Timing for reading data from flash memory and SRAM
Fig. 16.1.1 Timing for reading data from flash memory and SRAM
External
memory
data output
8
1: This applies when the external data bus has a width of 16 bits (BYTE = “L”).
External memory
output enable signal
(Read signal)
OE
E
External memory
chip select signal
CE, S
8
2: If data is output from the external memory before the falling edge of E,
there is a possi bility that
the tail
of
address collides wit
h the head of
data.
→
Refer to section
“(3) Precautions on memory connection.”
of
collides wit
.
→
Refer to section
“(3) Precautions on memory connection.”
address
8
3: If one of the external memory’s specifications is greater than
t
pzx
(E-DLZ/DHZ)
,
there is a possibility that
the tail
data
Address output and Data input
A
8
/
D
8
–A
15
/D
15
A
16
/D
0
–A
23
/D
7
8
1
t
en
(OE)
Address
t
pzx
(E-DLZ/DHZ)
t
su
(DL/DH-E)
: Specifications of the M37721
(The others are specifications of
external memory.)
t
a
(OE)
t
DF
, t
dis
(OE)
8
2
8
3
t
w(EL)
Data
t
en
(CE)
, t
en
(S)
Address
t
a
(CE)
, t
a
(S)
t
a
(AD)
, t
su
(A-DL/DH)
Note:
t
su(A-DL/DH)
: t
su(A-DL)
or t
su(A-DH)
t
pzx(E-DLZ/DHZ)
: t
pzx(E-DLZ)
or t
pzx(E-DHZ)
t
su(DL/DH-E)
: t
su(DL-E)
or t
su(DH-E)