
7721 Group User’s Manual
13-15
DMA CONT R OLLE R
13.2 Block description
13.2.11 DMAi mode register H
Figure 13.2.7 shows the structure of DMAi mode register H. Bits 0 and 1 are used in 1-bus cycle transfer.
For details, refer to section
“13.4.2 1-bus cycle transfer.”
Bits 6 and 7 are the bits for selecting the
continuous transfer mode. For details, refer to section
“13.5 Single transfer mode”
through section
“13.8
Link array chain transfer mode.”
(1)
Transfer source wait bit and Transfer destination wait bit (bits 4 and 5)
When each of these bits is set to “1,” 1-bus cycle in a DMA transfer consumes 3 cycles of
φ
, and
when cleared to “0,” 2 cycles of
φ
.
These bits are valid for the internal and external areas. In the DRAM area, however, 1-bus cycle
consumes 3 cycles of
φ
regardless of the states of these bits. (Refer to
“CHAPTER 14. DRAM
CONTROLLER.”
)
The wait bit (bit 2 at address 5E
16
) is invalid in DMA transfer. However, Ready function is still valid
in DMA transfer.
Fig. 13.2.7 Structure of DMAi mode register H
Bit
Bit name
At reset
5
0
RW
Functions
b7
b6
b5
b4
b3
0
b2
0
b1
b0
DMA0 mode register H (Address 1FCD
16
)
DMA1 mode register H (Address 1FDD
16
)
DMA2 mode register H (Address 1FED
16
)
DMA3 mode register H (Address 1FFD
16
)
Notes 1:
Set bit 0 to “0” in 2-bus cycle transfer.
2:
Bits 4 and 5 are valid to the external and internal areas. However, DRAM area is
always handled with “Wait” regardless of the contents of these bits.
The wait bit (bit 2 at address 5E
16
) is invalid in DMA transfer.
0
0
0 : From memory to I/O
1 : From I/O to memory
1
Refer to below.
2
0
3
0
4
0
6
0
7
RW
RW
Transfer direction select bit
(Used in 1-bus cycle transfer)
(Note 1)
I/O connection select bit
(Valid in 1-bus cycle transfer)
Fix these bits to “0.”
Transfer source wait bit
(Note 2)
Continuous transfer mode select
bits
0 0 : Single transfer
0 1 : Repeat transfer
1 0 : Array chain transfer
1 1 : Link array chain transfer
b7b6
RW
RW
RW
RW
0
0
RW
RW
Transfer destination wait bit
(Note 2)
0 : Wait
1 : No Wait
Setting for I/O connection select bit
Transfer method
1-bus cycle transfer
2-bus cycle transfer
External data bus width
8 bits
16 bits
I/O connection
D
0
–D
7
D
0
–D
15
(16-bit I/0
1 or 8-bit I/O
2)
D
0
–D
7
(8-bit I/O)
D
8
–D
15
(8-bit I/O)
Setting for I/O connection select bit
It may be either “0” or “1.”
0
0
0
1