4
4554 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
PERFORMANCE OVERVIEW
Function
136
0.5
s (at 6 MHz oscillation frequency, in high-speed through mode)
8192 words 10 bits
12288 words 10 bits
16384 words 10 bits
512 words 4 bits (including LCD display RAM 32 words 4 bits)
Eight independent I/O ports.
Input is examined by skip decision.
The output structure can be switched by software.
Port D7 is also used as CNTR0 pin.
Two independent output ports.
Ports D8 and D9 are also used as INT0 and INT1, respectively.
4-bit I/O port; A pull-up function, a key-on wakeup function and output structure can be switched
by software.
4-bit I/O port; A pull-up function, a key-on wakeup function and output structure can be switched
by software.
4-bit input port; Port P20–P23 are also used as SEG31–SEG28 pins.
4-bit input port; Port P30–P33 are also used as SEG27–SEG24 pins.
1-bit output; Port C is also used as CNTR1 pin.
8-bit programmable timer with a reload register and has an event counter.
8-bit programmable timer with a reload register.
8-bit programmable timer with a reload register and has an event counter.
8-bit programmable timer with two reload registers.
16-bit timer, fixed dividing frequency
1/2, 1/3 bias
2, 3, 4 duty
4
32
2r 3, 2r 2, r 3, r 2 (they can be switched by software.)
7 (two for external, five for timer)
1 level
8 levels
CMOS silicon gate
64-pin plastic molded QFP (64P6N)
–20 °C to 85 °C
2 to 5.5 V (It depends on the operation source clock, operation mode and oscillation frequency.)
2.5 to 5.5 V (It depends on the operation source clock, operation mode and oscillation frequency.)
2.8 mA (at room temperature, VDD = 5 V, f(XIN) = 6 MHz, f(XCIN) = 32 kHz, f(STCK) = f(XIN))
20
A (at room temperature, VDD = 5 V, f(XCIN) = 32 kHz)
0.1
A (at room temperature, VDD = 5 V)
Parameter
Number of basic instructions
Minimum instruction execution time
Memory sizes
Input/Output
ports
Timers
LCD control
circuit
Interrupt
Subroutine nesting
Device structure
Package
Operating temperature range
Supply
voltage
Power
dissipation
ROM
RAM
D0–D7
D8, D9
P00–P03
P10–P13
P20–P23
P30–P33
C
Timer 1
Timer 2
Timer 3
Timer 4
Timer 5
Selective bias value
Selective duty value
Common output
Segment output
Internal resistor for
power supply
Sources
Nesting
Mask ROM version
One Time PROM version
Active mode
Clock operating mode
At RAM back-up
M34554M8
M34554MC
M34554ED
I/O
Output
I/O
Input
Output