參數(shù)資料
型號: M34554MC-XXXFP
元件分類: 微控制器/微處理器
英文描述: 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PQFP64
封裝: 14 X 14 MM, 0.80 MM PITCH, PLASTIC, QFP-64
文件頁數(shù): 69/138頁
文件大小: 1082K
代理商: M34554MC-XXXFP
Rev.3.00
Aug 06, 2004
page 36 of 136
REJ03B0043-0300Z
4554 Group
Stop (state retained)
Operating
Bit 4 (T54) of timer 5
Prescaler output (ORCLK)
CNTR1 output auto-control circuit not selected
CNTR1 output auto-control circuit selected
D7(I/O)/CNTR0 input
CNTR0 input/output/D7 (input)
Timer LC control bit
Timer LC count source selection bit
CNTR1 output auto-control circuit
selection bit
D7/CNTR0 pin function selection bit
(Note 2)
0
1
0
1
0
1
0
1
Timer control register W6
at power down : state retained
at reset : 00002
W63
W62
W61
W60
CNTR1 output invalid
CNTR1 output valid
PWM signal “H” interval expansion function invalid
PWM signal “H” interval expansion function valid
Stop (state retained)
Operating
XIN input
Prescaler output (ORCLK) divided by 2
CNTR1 output control bit
PWM signal
“H” interval expansion function control bit
Timer 4 control bit
Timer 4 count source selection bit
0
1
0
1
0
1
0
1
W43
W42
W41
W40
W51
0
1
Not used
Timer 5 control bit
Timer 5 count value selection bits
0
1
0
1
W50
0
1
0
1
Timer control register W5
at power down : state retained
at reset : 00002
W53
W52
W51
W50
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: CNTR0 input is valid only when CNTR0 input is selected for the timer 1 count source.
This bit has no function, but read/write is enabled.
Stop (state initialized)
Operating
Count value
Underflow occurs every 8192 counts
Underflow occurs every 16384 counts
Underflow occurs every 32768 counts
Underflow occurs every 65536 counts
R/W
TAW4/TW4A
Timer control register W4
at power down : 00002
at reset : 00002
R/W
TAW5/TW5A
R/W
TAW6/TW6A
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