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參數(shù)資料
| 型號(hào)： | M34554MC-XXXFP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | 14 X 14 MM, 0.80 MM PITCH, PLASTIC, QFP-64 |
| 文件頁(yè)數(shù)： | 101/138頁(yè) |
| 文件大?。?/td> | 1082K |
| 代理商： | M34554MC-XXXFP |
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Rev.3.00
Aug 06, 2004
page 65 of 136
REJ03B0043-0300Z
4554 Group
D9/INT1 pin
Note [1] on bit 3 of register I2
When the input of the INT1 pin is controlled with the bit 3 of reg-
ister I2 in software, be careful about the following notes.
Depending on the input state of the D9/INT1 pin, the external 1 in-
terrupt request flag (EXF1) may be set when the bit 3 of register
I2 is changed. In order to avoid the occurrence of an unexpected
interrupt, clear the bit 1 of register V1 to “0” (refer to Figure 57)
and then, change the bit 3 of register I2.
In addition, execute the SNZ1 instruction to clear the EXF1 flag
to “0” after executing at least one instruction (refer to Figure
57).
Also, set the NOP instruction for the case when a skip is per-
formed with the SNZ1 instruction (refer to Figure 57).
LA
4
; (02)
TV1A
; The SNZ1 instruction is valid ...........
LA
8
; (12)
TI2A
; Control of INT1 pin input is changed
NOP
...........................................................
SNZ1
; The SNZ1 instruction is executed
(EXF1 flag cleared)
NOP
...........................................................
: these bits are not used here.
Fig. 57 External 1 interrupt program example-1
Note [2] on bit 3 of register I2
When the bit 3 of register I2 is cleared to “0”, the RAM back-up
mode is selected and the input of INT1 pin is disabled, be careful
about the following notes.
When the key-on wakeup function of INT1 pin is not used (regis-
ter K22 = “0”), clear bits 2 and 3 of register I2 before system
enters to the RAM back-up mode. (refer to Figure 58).
LA
0
; (002)
TI2A
; Input of INT1 disabled .....................
DI
EPOF
POF2
; RAM back-up
: these bits are not used here.
Fig. 58 External 1 interrupt program example-2
Note on bit 2 of register I2
When the interrupt valid waveform of the D9/INT1 pin is changed
with the bit 2 of register I2 in software, be careful about the fol-
lowing notes.
Depending on the input state of the D9/INT1 pin, the external 1 in-
terrupt request flag (EXF1) may be set when the bit 2 of register
I2 is changed. In order to avoid the occurrence of an unexpected
interrupt, clear the bit 1 of register V1 to “0” (refer to Figure 59)
and then, change the bit 2 of register I2.
In addition, execute the SNZ1 instruction to clear the EXF1 flag
to “0” after executing at least one instruction (refer to Figure
59).
Also, set the NOP instruction for the case when a skip is per-
formed with the SNZ1 instruction (refer to Figure 59).
LA
4
; (02)
TV1A
; The SNZ1 instruction is valid ...........
LA
12
; (12)
TI2A
; Interrupt valid waveform is changed
NOP
...........................................................
SNZ1
; The SNZ1 instruction is executed
(EXF1 flag cleared)
NOP
...........................................................
: these bits are not used here.
Fig. 59 External 1 interrupt program example-3
17
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相關(guān)代理商/技術(shù)參數(shù) |
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| M34556G8FP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER |
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