Rev.2.00
Jul 27, 2004
page 35 of 159
REJ03B0091-0200Z
4524 Group
W21
0
1
Timer 1 underflow signal divided by 2 output
Timer 2 underflow signal divided by 2 output
Stop (state retained)
Operating
Count source
System clock (STCK)
Prescaler output (ORCLK)
Timer 1 underflow signal (T1UDF)
PWM signal (PWMOUT)
CNTR0 output control bit
Timer 2 control bit
Timer 2 count source selection bits
0
1
0
1
W20
0
1
0
1
Timer control register W2
at power down : state retained
at reset : 00002
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: This function is valid only when the timer 1 count start synchronous circuit is selected (I10=“1”).
3: This function is valid only when the timer 3 count start synchronous circuit is selected (I20=“1”).
4: Port C output is invalid when CNTR1 input is selected for the timer 3 count source.
W23
W22
W21
W20
0
1
Stop (state initialized)
Operating
Prescaler control bit
Timer control register PA
W
TPAA
at power down : 02
at reset : 02
PA0
W11
0
1
Timer 1 count auto-stop circuit not selected
Timer 1 count auto-stop circuit selected
Stop (state retained)
Operating
Count source
Instruction clock (INSTCK)
Prescaler output (ORCLK)
Timer 5 underflow signal (T5UDF)
CNTR0 input
Timer 1 count auto-stop circuit selection
bit (Note 2)
Timer 1 control bit
Timer 1 count source selection bits
0
1
0
1
W10
0
1
0
1
Timer control register W1
R/W
TAW1/TW1A
at power down : state retained
at reset : 00002
W13
W12
W11
W10
W31
0
1
Timer 3 count auto-stop circuit not selected
Timer 3 count auto-stop circuit selected
Stop (state retained)
Operating
Count source
PWM signal (PWMOUT)
Prescaler output (ORCLK)
Timer 2 underflow signal (T2UDF)
CNTR1 input
Timer 3 count auto-stop circuit selection
bit (Note 3)
Timer 3 control bit
Timer 3 count source selection bits
(Note 4)
0
1
0
1
W30
0
1
0
1
Timer control register W3
at power down : state retained
at reset : 00002
W33
W32
W31
W30
R/W
TAW2/TW2A
R/W
TAW3/TW3A
Table 10 Timer related registers