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參數(shù)資料
| 型號： | M34524MC-XXXFP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 6 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | 14 X 14 MM, 0.80 MM PITCH, PLASTIC, QFP-64 |
| 文件頁數(shù)： | 140/163頁 |
| 文件大小： | 1235K |
| 代理商： | M34524MC-XXXFP |
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Rev.2.00
Jul 27, 2004
page 76 of 159
REJ03B0091-0200Z
4524 Group
D8/INT0 pin
Note [1] on bit 3 of register I1
When the input of the INT0 pin is controlled with the bit 3 of reg-
ister I1 in program, be careful about the following notes.
Depending on the input state of the D8/INT0 pin, the external 0 in-
terrupt request flag (EXF0) may be set when the bit 3 of register
I1 is changed. In order to avoid the occurrence of an unexpected
interrupt, clear the bit 0 of register V1 to “0” (refer to Figure 65)
and then, change the bit 3 of register I1.
In addition, execute the SNZ0 instruction to clear the EXF0 flag
to “0” after executing at least one instruction (refer to Figure
65).
Also, set the NOP instruction for the case when a skip is per-
formed with the SNZ0 instruction (refer to Figure 65).
LA
4
; (02)
TV1A
; The SNZ0 instruction is valid ...........
LA
8
; (12)
TI1A
; Control of INT0 pin input is changed
NOP
...........................................................
SNZ0
; The SNZ0 instruction is executed
(EXF0 flag cleared)
NOP
...........................................................
: these bits are not used here.
Fig. 65 External 0 interrupt program example-1
Note [2] on bit 3 of register I1
When the bit 3 of register I1 is cleared, the power down function
is selected and the input of INT0 pin is disabled, be careful about
the following notes.
When the input of INT0 pin is disabled, invalidate the key-on
wakeup function of INT0 pin (register K20 = “0”) before system
goes into the power down mode. (refer to Figure 66).
LA
0
; (02)
TK2A
; INT0 key-on wakeup invalid ...........
DI
EPOF
POF2
; RAM back-up
: these bits are not used here.
Fig. 66 External 0 interrupt program example-2
Note on bit 2 of register I1
When the interrupt valid waveform of the D8/INT0 pin is changed
with the bit 2 of register I1 in program, be careful about the fol-
lowing notes.
Depending on the input state of the D8/INT0 pin, the external 0 in-
terrupt request flag (EXF0) may be set when the bit 2 of register
I1 is changed. In order to avoid the occurrence of an unexpected
interrupt, clear the bit 0 of register V1 to “0” (refer to Figure 67)
and then, change the bit 2 of register I1.
In addition, execute the SNZ0 instruction to clear the EXF0 flag
to “0” after executing at least one instruction (refer to Figure
67).
Also, set the NOP instruction for the case when a skip is per-
formed with the SNZ0 instruction (refer to Figure 67).
LA
4
; (02)
TV1A
; The SNZ0 instruction is valid ...........
LA
12
; (12)
TI1A
; Interrupt valid waveform is changed
NOP
...........................................................
SNZ0
; The SNZ0 instruction is executed
(EXF0 flag cleared)
NOP
...........................................................
: these bits are not used here.
Fig. 67 External 0 interrupt program example-3
16
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