參數(shù)資料
型號： M34507M4-XXXFP
元件分類： 微控制器/微處理器
英文描述： 4-BIT, MROM, MICROCONTROLLER, PDSO24
封裝： 5.30 X 10.10 MM, 0.80 MM PITCH, PLASTIC, SSOP-24
文件頁數(shù)： 32/117頁
文件大小： 937K
代理商： M34507M4-XXXFP
4507 Group
Rev.3.01
2005.02.04
page 19 of 111
REJ03B0107-0301
(6) Interrupt control registers
Interrupt control register V1
Interrupt enable bits of external 0, timer 1 and timer 2 are as-
signed to register V1. Set the contents of this register through
register A with the TV1A instruction. The TAV1 instruction can be
used to transfer the contents of register V1 to register A.
Interrupt control register V2
The A/D interrupt enable bit is assigned to register V2. Set the
contents of this register through register A with the TV2A instruc-
tion. The TAV2 instruction can be used to transfer the contents of
register V2 to register A.
Table 6 Interrupt control registers
V13
V12
V11
V10
V23
V22
V21
V20
Not used
A/D interrupt enable bit
Not used
Interrupt control register V1
Timer 2 interrupt enable bit
Timer 1 interrupt enable bit
Not used
External 0 interrupt enable bit
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: These instructions are equivalent to the NOP instrucion.
Interrupt disabled (SNZT2 instruction is valid)
Interrupt enabled (SNZT2 instruction is invalid) (Note 2)
Interrupt disabled (SNZT1 instruction is valid)
Interrupt enabled (SNZT1 instruction is invalid) (Note 2)
This bit has no function, but read/write is enabled.
Interrupt disabled (SNZ0 instruction is valid)
Interrupt enabled (SNZ0 instruction is invalid) (Note 2)
This bit has no function, but read/write is enabled.
Interrupt disabled (SNZAD instruction is valid)
Interrupt enabled (SNZAD instruction is invalid) (Note 2)
This bit has no function, but read/write is enabled.
0
1
0
1
0
1
0
1
R/W
at RAM back-up : 00002
at reset : 00002
R/W
at RAM back-up : 00002
at reset : 00002
Interrupt control register V2
R/W
at RAM back-up : 00002
at reset : 00002
0
1
0
1
0
1
0
1
(7) Interrupt sequence
Interrupts only occur when the respective INTE flag, interrupt en-
able bits (V10, V12, V13, V22), and interrupt request flag are “1.”
The interrupt actually occurs 2 to 3 machine cycles after the cycle
in which all three conditions are satisfied. The interrupt occurs after
3 machine cycles only when the three interrupt conditions are sat-
isfied on execution of other than one-cycle instructions (Refer to
Figure 16).
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