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15. Timer (Timer A)
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15.1 Timer A
Figure 15.3 shows a block diagram of the timer A. Figures 15.4 to 15.7 show registers associated with the
timer A.
The timer A supports the following four modes. Except in event counter mode, all timers A0 to A4 have the
same function. The TMOD1 and TMOD0 bits in the TAiMR register (i=0 to 4) determine which mode is
used.
Timer mode: The timer counts an internal count source.
Event counter mode: The timer counts an external pulse or an overflow and underflow of other timers.
One-shot timer mode: The timer outputs one valid pulse until a counter value reaches "000016".
Pulse width modulation mode: The timer continuously outputs desired pulse widths.
Table 15.1 lists TAiOUT pin settings when used as an output. Table 15.2 lists TAiIN and TAiOUT pin settings
when used as an input.
TAiS
Increment / decrement
TAi
Addresses
TAj
TAk
Timer A0 034716 034616 Timer A4 Timer A1
Timer A1 034916 034816 Timer A0 Timer A2
Timer A2 034B16 034A16 Timer A1 Timer A3
Timer A3 034D16 034C16 Timer A2 Timer A4
Timer A4 034F16 034E16 Timer A3 Timer A0
Select Count Source
Timer Mode (gate function):
TMOD1 and TMOD0=00, MR2=1
Timer Mode
:TMOD1 and TMOD0=00, MR2=0
One-Shot Timer Mode :TMOD1 and TMOD0=10
Pulse Width Modulation Mode
:TMOD1 and TMOD0=11
f1
f8
f2n(1)
TAiIN
Event Counter Mode:TMOD1 and TMOD0=01
fC32
Select clock
TAj Overflow(2)
Pulse Output
Toggle Flip Flop
TAiOUT
Always decrement except
in event counter mode
8 low-
order
bits
High-Order Bits of Data Bus
Reload Register
Counter
Low-Order Bits of Data Bus
TAiUD
Decrement
TAk Overflow(2)
Polarity
Selector
00
01
11
10
TCK1 and
TCK0
TB2 Overflow(2)
00
01
10
11
TAiTGH and TAiTGL
11
01
00
0
1
MR2
TMOD1 and TMOD0
NOTES:
1. The CNT3 to CNT0 bits in the TCSPR register select
no division (n=0) or divide-by-2n (n=1 to 15).
2. Overflow or underflow signal
TCK1 and TCK0, TMOD1 and TMOD0, MR2 and MR1 : Bits in the TAiMR register
TAiTGH and TAiTGL : Bits in the ONSF register if i=0 or bits in the TRGSR register if i=1 to 4
TAiS : Bits in the TABSR register
TAiUD : Bits in the UDF register
TMOD1 and TMOD0,
MR2
i=0 to 4
j=i-1, except j=4 if i=0
k=i+1, except k=0 if i=4
8 high-
order
bits
Figure 15.3 Timer A Block Diagram