![](http://datasheet.mmic.net.cn/30000/M30855FHTGP_datasheet_2359399/M30855FHTGP_331.png)
Page 308
4
9
4
f
o
5
0
2
,
1
0
.
l
u
J
3
0
.
1
.
v
e
R
3
0
1
0
-
7
3
0
B
9
0
J
E
R
22. Intelligent I/O (Communication Function)
)
T
5
8
/
C
2
3
M
,
5
8
/
C
2
3
M
(
p
u
o
r
G
5
8
/
C
2
3
M
22.4.1 Clock Synchronous Serial I/O Mode (Communication Units 0 and 1)
In clock synchronous serial I/O mode, data is transmitted and received with the transfer clock. f8 or f2n
can be selected as the communication unit 0 transfer clock. f8, f2n or the clock generated by channels 0
and 3 can be selected as the communication unit 1 transfer clock.
Table 22.12 lists specifications of clock synchronous serial I/O mode for the communication units 0 and
1. Tables 22.13 and 22.14 list clock settings. Table 22.15 lists register settings. Tables 22.16 to 22.19
list pin settings. Figure 22.29 shows an example of transmit and receive operation.
Table 22.12 Clock Synchronous Serial I/O Mode Specifications (Communication Units 0 and 1)
Item
Specification
Transfer Data Format
Transfer data :
8 bits long
Transfer Clock(1)
See Tables 22.13 and 22.14
Transmit Start Condition
Set registers associated with the waveform generating function, the GiMR register and
GiERC register. Then, set as is written below after waiting at least one transfer clock cycle.
Set the TE bit in the GiCR register to "1" (transmit enable)
Set the TI bit in the GiCR register to "0" (data in the GiTB register)
Receive Start Condition
Set registers associated with the waveform generating function, the GiMR register and
GiERC register. Then, set as is written below after waiting at least one transfer clock cycle.
Set the RE bit in the GiCR register to "1" (receive enable)
Set the TE bit to "1" (transmit enable)
Set the TI bit to "0" (data in the GiTB register)
Interrupt Request
While transmitting, one of the following conditions can be selected to set the SIOiTR
bit to "1" (interrupt requested) (see Figure 11.14) :
_ The IRS bit in the GiMR register is set to "0" (no data in the GiTB register) and
data is transferred to the transmit register from the GiTB register
_ The IRS bit is set to "1" (transmission completed) and data transfer from the
transmit register is completed
While receiving, the following condition can be selected to set SIOiRR bit is set to "1"
(data reception is completed):
Data is transferred from the receive register to the GiRB register
Error Detection
Overrun error(2)
This error occurs, when the next data reception is started and the 8th bit of the next
data is received before reading the GiRB register
Selectable Function
LSB first or MSB first
Select either bit 0 or bit 7 to transmit or receive data
ISTxDi and ISRxDi I/O polarity inverse
ISTxDi pin output level and ISRxDi pin input level are inversed
NOTES:
1. In clock synchronous serial I/O mode, set the RSHTE bit in the GiERC register (i=0, 1) to "1" (receive
shift operation enabled).
2. When an overrun error occurs, the GiRB register is indeterminate.
When the OPOL bit in the GiCR register is set to "0" (ISTxD output polarity not inversed), the ISTxDi pin
puts in a high-level ("H") signal output after selecting operating mode until transfer starts. When the OPOL
bit is set to "1" (ISTxD output polarity inversed), the ISTxDi pin puts in a low-level ("L") signal output.
Table 22.13 Clock Settings (Communication Unit 0)
Transfer Clock
G0MR Register
CCS Register
CKDIR Bit
CCS0 Bit
CCS1 Bit
f8
01
1
f2n(1)
00
1
Input from ISCLK0
1
-
NOTES:
1. The CNT3 to CNT0 bits in the TCSPR register select no division (
n=0) or divide-by-2n (n=1 to 15).