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M30245 Group
DMA
Rev.2.00
Oct 16, 2006
page 101 of 264
REJ03B0005-0200
Table 1.37. DMAC specifications
Item
Specification
No. of channels
4 (cycle steal method)
Transfer memory space
From any address in the 1M bytes space to a fixed address
[002016 to 003F16 and 018016 to 019F16] cannot be accessed)
Maximum No. of bytes transferred
128K bytes (with 16-bit transfers) or 64K bytes (with 8-bit transfers)
DMA request factors (Note)
Falling edge of INT0, INT1, INT2 or both edges
Timer A0 to Timer A4 interrupt requests
UART0-3 transfer and receive interrupt requests
A/D conversion interrupt request
Software triggers
Serial Sound Interface 0-1 transmit and receive interrupt
Channel priority
High to low priority: DMA0, DMA1, DMA2, DMA3
Transfer unit
8 bits or 16 bits
Transfer address direction
Forward/fixed (forward direction cannot be specified for both source and
destination simultaneously)
Transfer mode
Single transfer mode
After the transfer counter underflows, the DMA enable bit is set to "0"
and the DMAC becomes inactive
Repeat transfer mode
After the transfer counter underflows, the value of the transfer counter
reload register is reloaded to the transfer counter. The DMAC remains
active unless a "0" is written to the DMA enable bit.
DMA interrupt request generation
timing
When an underflow occurs in transfer counter
Active
When the DMA enable bit is set to "1", the DMAC is active.
When the DMAC is active, data transfer starts each time the DMA transfer
request signal occurs.
Inactive
When the DMA enable bit is set to "0", the DMAC is inactive
After the transfer counter underflows in single transfer mode.
Forward address pointer and reload
timing for transfer counter
When data transfer starts immediately after turning DMAC active, or when the
transfer counter underflows in repeat transfer mode, the value of the source
pointer or destination pointer (whichever is specified for forward direction) is
reloaded to the forward direction address pointer, and the value of the transfer
counter reload register is reloaded to the transfer counter.
Writing to register
Registers specified for forward direction transfer are always write enabled.
Registers specified for fixed address transfer are write-enabled when the DMA
enable bit is "0".
Reading the register
Can be read at any time. However, when the DMA enable bit is "1", reading the
register set-up as the forward register is the same as reading the value of the
forward address pointer.
Note: DMA transfer is not effective to any interrupts. DMA transfer is not affected by the interrupt enable flag (I flag) or
by the interrupt priority level.
DM Atriggers
From a fixed address to any address in the 1M bytes space
From a fixed address to a fixed address (note that DMA related registers
USB triggers, selectable by endpoint