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M30245 Group
Parallel I/O Mode
Rev.2.00
Oct 16, 2006
page 207 of 264
REJ03B0005-0200
ROM code protect function
To prevent the contents of the flash memory from being read out or rewritten too easily, the device incorporates a
ROM code protect function for use in parallel I/O mode. The ROM code protect function prevents reading out or
modifying the contents of the flash memory by using the ROM code protect control register (0FFFFF16) during
parallel I/O mode. Figure 1.157 shows the ROM code protect control address. (This address exists in the user
ROM area.)
If one pair of ROM code protect bits is set to "0", ROM code protect is turned on so that the contents of the flash
memory are protected against being read out or modified. The ROM code protect function is implemented in two
levels. If level 2 is selected, the flash memory is protected even against readout by a shipment inspection LSI
tester, etc. If both level 1 and level 2 are selected, level 2 is selected by default.
If both of the two ROM code protect reset bits are set to "00," the ROM code protect function is turned off so that the
contents of the flash memory can be read out or modified. Once ROM code protect is turned on, the contents of the
ROM code protect reset bits cannot be modified in parallel I/O mode. Use the serial I/O mode or another mode to
rewrite the contents of the ROM code protect reset bits.
Bit Symbol
Bit Name
Function
Reserved
ROMCP2
ROMCR
ROMCP1
ROM code protect level 2
set bit (Note 1, 2)
ROM code protect reset bit
(Note 3)
ROM code protect level 1
set bit (Note 1)
Always set to "1"
b3 b2
0 0 : Protect enable
0 1 : Protect enable
1 0 : Protect enable
1 1 : Protect enable
b5 b4
0 0 : No protect set bit
0 1 : Protect set bit active
1 0 : Protect set bit active
1 1 : Protect set bit active
b7 b6
0 0 : Protect enable
0 1 : Protect enable
1 0 : Protect enable
1 1 : Protect enable
Symbol
ROMCP
Address
0FFFFF
16
ROM code protect control register
b7
b5
b6
b4
b3
b2
b1
b0
Note 1: When ROM code protect is turned on, the on-chip flash memory is
protected against readout or modification in parallel input/output mode.
Note 2: When ROM code protect level 2 is turned on, ROM code readout by a
shipment inspection LSI tester, etc, is inhibited.
Note 3: The ROM code protect reset bits can be used to turn off ROM code protect
levels 1 and 2. However, because these bits cannot be changed in parallel
input/output mode, they need to be rewritten in serial input/output or some
other mode.
11
When reset
FF
16
Figure 1.157. ROM code protect control register