參數(shù)資料
型號: M30240S9-XXXFP
廠商: Mitsubishi Electric Corporation
英文描述: 16 Characters x 2 Lines, 5x7 Dot Matrix Character and Cursor
中文描述: 單片16位CMOS微機(jī)
文件頁數(shù): 43/142頁
文件大?。?/td> 1637K
代理商: M30240S9-XXXFP
1-43
Mitsubishi microcomputers
M30240 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
Frequency Synthesizer Circuit
The FSC0 bit in the FSC Control Register enables the frequency synthesizer block. When disabled
(FSC0 = “0”), f
VCO
is held at either a high or low state. When the frequency synthesizer control bit is
active (FSC0 = “1”), a lock status (LS = “1”) indicates that f
SYN
and f
VCO
are the correct frequency. The
LS and FSCO control bits in the FSC Control register are shown in Figure 1.27.
When using the frequency synthesizer, a low-pass filter must be connected to the LPF pin.
Once the frequency synthesizer is enabled, a delay of 2-5ms is recommended before the output of the
frequency synthesizer is used. This is done to allow the output to stabilize. It is also recommended that
none of the registers be modified once the frequency synthesizer is enabled as it will cause the output
to be temporarily (2-5ms) unstable. The MCU clock source is selected via the Frequency Synthesizer
Clock Control register (FSCCR). See Figure 1.28.
Note: None of the registers must be written to once the frequency synthesizer is enabled and used as
the system clock source (FSCCR register, address 03DB
16
, bit ‘0’ set to ‘1’) because it will cause the
output of the PLL to freeze. Switch system back to f(X
IN
) and disable before modifying PLL registers.
Figure 1.27: Frequency Synthesizer Control Register (FSC)
Figure 1.28: Frequency Synthesizer Clock Control Register (FSCCR)
Frequency Synthesizer Control Register
Symbol
FSC
Address
03DC
16
When reset
60
16
Bit name
Bit symbol
b7
b6
b5
b4
0 0
b3
b2
b1
b0
0 : Disable
1 : Enabled
VCO0
FSE
VCO Gain Control
Function
Bit 2
0
0
1
1
Bit 1
0:
1:
0:
1:
Lowest Gain (Note 1)
Low Gain
High Gain
Highest Gain
Frequency Synthesizer Enable
W
R
Reserved bit
Must always be set to "0"
VCO1
CHG0
CHG1
LPF Current Control
Bit 6
0
0
1
1
0:
1:
Bit 5
0:
1:
0:
1:
Unlocked
Locked
Disabled
Low Current
Intermediate Current (Note 1)
High Current
LS
Frequency Synthesizer
Lock Status
Note 1: Recommended
Frequency Synthesizer Clock Control Register
Symbol
FSCCR
Address
03DB
16
When reset
00
16
Bit name
Bit symbol
b7
0 0 0 0 0 0 0
b6
b5
b4
b3
b2
b1
b0
0 : Xin
1 : fsyn
FSCCR0
Function
W
R
Reserved
Must always be set to "0"
Clock source selection
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