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參數(shù)資料
| 型號： | M30240S9-XXXFP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 16 Characters x 2 Lines, 5x7 Dot Matrix Character and Cursor |
| 中文描述： | 單片16位CMOS微機(jī) |
| 文件頁數(shù)： | 101/142頁 |
| 文件大?。?/td> | 1637K |
| 代理商： | M30240S9-XXXFP |
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1-101
Mitsubishi microcomputers
M30240 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Preliminary Specifications REV. E
Specifications in this manual are tentative and subject to change
UART0 through UART2
Figure 1.90: Typical receive timing in UART mode
2.23.2.1 Sleep mode (UART0, UART1)
This mode is used to transfer data between specific microcomputers among multiple microcomputers con-
nected using UARTi. The sleep mode is selected when the sleep select bit (bit 7 at addresses 03A0
16
,
03A8
16
) is set to “1” during reception. In this mode, the unit performs receive operation when the MSB of the
received data = “1” and does not perform receive operation when the MSB = “0”.
2.23.2.2 Function for switching serial data logic (UART2)
When the data logic select bit (bit 6 of address 037D
16
) is assigned 1, data is inverted in writing to the trans-
mission buffer register or reading the reception buffer register. Figure 1.91 shows the example of timing for
switching serial data logic.
Figure 1.91: Timing for switching serial data logic
D
0
Start bit
Sampled “L”
Receive data taken in
BRGi count
source
Receive enable bit
RxDi
Transfer clock
Receive
complete flag
RTSi
Stop bit
“1”
“0”
“H”
“L”
“1”
“0”
“1”
The above timing applies to the following settings :
Parity is disabled.
One stop bit.
RTS function is selected.
Receive interrupt
request bit
“0”
Transferred from UARTi receive register to
UARTi receive buffer register
Reception triggered when transfer clock
is generated by falling edge of start bit
D
7
D
1
Cleared to “0” when interrupt request is accepted, or cleared by software
Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit)
ST : Start bit
P : Even parity
SP : Stop bit
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
ST
SP
ST
D3
D4
D5
D6
D7
P
D0
D1
D2
Transfer clock
TxD
2
(no reverse)
TxD
2
(reverse)
“H”
“L”
“H”
“L”
“H”
“L”
When LSB first, parity enabled, one stop bit
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M30240SA | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
| M30240SA-XXXFP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
| M30240SC | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
| M30240SC-XXXFP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
| M30245 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
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