參數(shù)資料
型號(hào)： M24C01-RMB3T/S
廠商： STMICROELECTRONICS
元件分類： PROM
英文描述： 128 X 8 I2C/2-WIRE SERIAL EEPROM, DSO8
封裝： 2 X 3 MM, MLP-8
文件頁(yè)數(shù)： 30/33頁(yè)
文件大?。?/td> 278K
代理商： M24C01-RMB3T/S
Summary description
M24C16, M24C08, M24C04, M24C02, M24C01
1
Summary description
These IC-compatible electrically erasable programmable memory (EEPROM) devices are
organized as 2048/1024/512/256/128 x 8 (M24C16, M24C08, M24C04, M24C02 and
M24C01).
In order to meet environmental requirements, ST offers these devices in ECOPACK
packages.
ECOPACK packages are Lead-free and RoHS compliant.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
Figure 1.
Logic diagram
IC uses a two-wire serial interface, comprising a bi-directional data line and a clock line.
The devices carry a built-in 4-bit Device Type Identifier code (1010) in accordance with the
IC bus definition.
The device behaves as a slave in the IC protocol, with all memory operations synchronized
by the serial clock. Read and Write operations are initiated by a Start condition, generated
by the bus master. The Start condition is followed by a Device Select Code and Read/Write
bit (RW) (as described in Table 3), terminated by an acknowledge bit.
When writing data to the memory, the device inserts an acknowledge bit during the 9th bit
time, following the bus master’s 8-bit transmission. When data is read by the bus master, the
bus master acknowledges the receipt of the data byte in the same way. Data transfers are
terminated by a Stop condition after an Ack for Write, and after a NoAck for Read.
Table 2.
Signal names
E0, E1, E2
Chip Enable
SDA
Serial Data
SCL
Serial Clock
WC
Write Control
VCC
Supply Voltage
VSS
Ground
AI02033
3
E0-E2
SDA
VCC
M24Cxx
WC
SCL
VSS
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