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參數資料
| 型號： | M-ORT82G51BM680-DB |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| 封裝： | PLASTIC, FBGA-680 |
| 文件頁數： | 4/94頁 |
| 文件大小： | 2104K |
| 代理商： | M-ORT82G51BM680-DB |
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Lattice Semiconductor
ORCA ORT82G5 Data Sheet
12
Figure 2. Top Level Block Diagram, Embedded Core Logic (Channel AA)
The Embedded Core provides transceiver functionality for eight serial data channels and is organized into two
quads, each supporting four channels. Each channel is identied by both a quad identier [A:B] and a channel
identier [A:D]. The data channels can operate independently or they can be combined together (aligned) to
achieve higher bit rates. The mode operation of the core is dened by a set of control registers, which can be writ-
ten through the system bus interface. Also, the status of the core is stored in a set of status registers, which can be
read through the system bus interface.
The transmitter section for each channel accepts 40 bits of data or 32 bits of data and eight control/status bits from
the FPGA logic and optionally encodes the data using 8b/10b encoding. It also accepts the low-speed reference
clock at the REFCLK input and uses this clock to synthesize the internal high-speed serial bit clock. The data is
then serialized and the serialized data are available at the differential CML output terminated in 86 to drive either
an optical transmitter or coaxial media or circuit board/backplane.
The receiver section receives high-speed serial data at its differential CML input port. These data are fed to the
clock recovery section which generates a recovered clock and retimes the data. The retimed data are also deseri-
alized, optionally 8b/10b decoded and presented as parallel data to the FPGA logic. Two-phase receive byte clocks
are available synchronous with the parallel words. The receiver also optionally recognizes the comma characters or
code violations and aligns the bit stream to the proper word boundary.
8b/10b Encoding and Decoding
In 8b/10b mode, the FPGA logic will receive/transmit 32 bits of data and 4 K_CTRL bits from/to the embedded
core. In the transmit direction, four additional input bits force negative disparity coding. The embedded core logic
will encode the data to or decode the data from a 10-bit format according to the FC-PH ANSI X3.230:1994 stan-
dard (which is also the encoding used by the IEEE 802.3ae Ethernet standard). This encoding/decoding scheme
also allows for the transmission of special characters and supports error detection.
Following the denitions and conventions used in dening the 8b/10b coding rules, each valid coded character has
a name corresponding to its 8-bit binary value:
Common Logic, Quad A
Channel AB
.
..
Channel BD
Backplane
Serial
Links
Receive Channel AA
2:1 MUX
(x40)
DEMUX
Block
Link State
Machine
RX SER-
DES Block
Multi -
Channel
Alignment
Block
TX SERDES
Block
Interface and
MUX Block
Transmit Channel AA
RCK78A
TCK78A
MRWDAA[39:0]
CV_SELAA
RWCKAA
RSYS_CLK_A1
TSYS_CLK_AA
TWDAA[31:0]
TCOMMAA[3:0]
.
FPGA
Logic
HDOUT[P:N]_AA
2
HDIN[P:N]_AA
REFCLK[P:N]_A
2
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