參數(shù)資料
型號： M-ORT82G51BM680-DB
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： FPGA
英文描述： FPGA, 1296 CLBS, 333000 GATES, PBGA680
封裝： PLASTIC, FBGA-680
文件頁數(shù)： 38/94頁
文件大?。?/td> 2104K
代理商： M-ORT82G51BM680-DB
Lattice Semiconductor
ORCA ORT82G5 Data Sheet
43
Figure 24. “Near End” vs. “Far End” Loopback
The loopback mode can also be characterized by the physical location of the loopback connection. There are four
possible loopback modes supported by the Embedded Core logic:
High-speed serial loopback at the CML buffer interface (near end)
Parallel loopback at the SERDES boundary (far end)
Parallel loopback at MUX/DEMUX boundary excluding SERDES (near end)
Loopback testing using the PRBS generator/checker
The four loopback modes are described in more detail in the following sections. As noted earlier, other specialized
loopback modes can be obtained by conguration of the FPGA logic or by connections external to the FPSC.
High-Speed Serial Loopback at the CML Buffer Interface
The high-speed serial loopback mode has the serial transmit signals looped back internally to the serial receive cir-
cuitry. The internal loopback path is from the input connection to the transmit CML buffer to the output connection
from the receive CML buffer. The data are sourced on the TWDxx[31:0], TCOMMAxx[3:0] and TBIT9xx[3:0] signal
lines and received on the MRWDxx[39:0] signal lines. The serial loopback path does not include the high-speed
input and output buffers. If TESTEN_xx is set, the HDOUTP_xx and HDOUTN_xx outputs are active in this mode
while the CML input buffers are powered down. The device is otherwise in its normal mode of operation. This mode
is normally used for tests where the data source and destination are on the same card and is the basic loopback
path shown earlier in Figure 24(a).
ORT82G5 Device Under Test (DUT)
CML
Buffer
CML
Buffer
HDIN[P:N]_xx
2
Non-Functional
Embedded Core
FPGA Logic
40
MRWDxx[39:0]
32
4
Receive
Transmit
TWDxx[31:0]
TCOMMAxx[3:0]
TBIT9xx[3:0]
HDOUT[P:N]_xx
2
Data
Checking
Data
Generation
n
m
{
Active
(to Eye Diagram
Measurement or
remote System
Card)
Test Equipment
or Logic on Local
System Card
(a) “Near End” Loopback
High Speed
Serial Loopback
Connection
ORT82G5 Device Under Test (DUT)
Data
Generation
Data
Checking
2
HDIN[P:N]_xx
HDOUT[P:N]_xx
{
n
m
Non-Functional
Active
(to Logic on
Local System
Card)
(b) “Far End” Loopback
FPGA Logic
40
MRWDxx[39:0]
Receive
4
Transmit
TWDxx[31:0]
TCOMMAxx[3:0]
TBIT9xx[3:0]
32
DE
MUX
8B/10B SERDES
CML
Buffer
8B/10B
CML
Buffer
SERDES Block
Parallel
Loopback
Connection
SERDES
Embedded Core
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