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| 型號： | M-ORT82G51BM680-DB |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| 封裝： | PLASTIC, FBGA-680 |
| 文件頁數(shù)： | 10/94頁 |
| 文件大?。?/td> | 2104K |
| 代理商： | M-ORT82G51BM680-DB |
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Lattice Semiconductor
ORCA ORT82G5 Data Sheet
18
Figure 6. Basic Logic Blocks, Receive Path, Single Channel (Typical Reference Clock Frequency)
Each channel provides its own received clock, received data and K-character detect signals to the FPGA logic.
Incoming data from multiple channels can be aligned using comma (/K/) characters or /A/ character (as specied
either in Fibre Channel specications or in IEEE 802.3ae for XAUI based interfaces). If the 8b/10b decoders are
bypassed, then 40-bit data streams are passed to the FPGA logic. No channel alignment can be done in this
8b/10b bypass mode.
Each channel also contains a PRBS checker which can be used as a built-in Bit Error Rate Tester (BERT) during
loopback testing. When enabled, it produces a one-bit PRBSCHK_xx (where xx stands for one of the letter pairs
[AA,...,BD]) output to indicate whether there was an error in the received data. Detailed descriptions of data syn-
chronization, of the SERDES, DEMUX and Multi-Channel Alignment blocks and of the Fibre Channel and XAUI
state machines are given in following sections. Receive clock distribution and the PRBS operation are described in
later sections of this data sheet.
Synchronization
The ORT82G5 SERDES RX logic performs four levels of synchronization on the incoming serial data stream. Each
level builds upon the previous, providing rst bit, then byte (character), then channel (32-bit word), and nally multi-
channel alignment. Each step is described functionally in the following paragraphs. The details of the logical imple-
mentations are described in subsequent sections.
Bit alignment is the task of the Clock/Data Recovery (CDR) block. This block utilizes a PLL that locks to the transi-
tions in the incoming high-speed serial data stream, and outputs the extracted clock as well as the data. If the PLL
is unable to lock to the serial data stream, it instead locks to REFCLK[A:B] to stabilize the voltage-controlled oscil-
lator (VCO), and periodically switches back to the serial data stream to again attempt synchronization. This pro-
REFCLKP_[A:B]
REFCLKN_[A:B]
REFCLK
Buffer
MUX
RCK78[A:B]
78.125 MHz
RCKSEL[0:1][A:B]
Logic Common to Quad
From other 3
channels
To other 3
channels
From Control
Register
{
PLL
PRBS Checker
CML
Buffer
1:10
DEMUX
8B/10B
Encode
r (with
bypass)
HDINP_xx
HDIN_xx
CDR
Byte
Align
RX SERDES Block
XAUI
State
Machine
1:4
DEMUX
(x 10)
156.25 MHz
FIFO
Multi-
Channel
Alignment
FPGA
Logic
Backplane
Serial
Link
RWCKxx
78.125 MHz
Multi-Channel
Alignment Block
78.125 MHz
78.125 MHz Clock
RALIGNxx[3:0]
Align Character Detect
4
RWBIT8xx[3:0]
4 bits k-control
32
RWDxx[31:0]
32-bit data
RSYS_CLK_x#
78.125 MHz
2:1
MUX
(x40)
MRWDxx[39:0]
CV_SELxx
4
RWBIT9xx[3:0]
40
36
32-bit data
4 bits k-ctrl
Synchronization
Status bits
See Table 8
Fibre Channel State
Machine
SRBD_xx[0:9]
DEMUX
Block
SCVxx
312.5 MHz
Clocks
10
2
SBYTSYNC_xx
SWDSYNC_xx
Note: xx= [AA, AB, ... BD]
x# = [A1, ...B2]
3
FPGA
Logic
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