參數(shù)資料
型號(hào)： M-ORT82G51BM680-DB
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： FPGA
英文描述： FPGA, 1296 CLBS, 333000 GATES, PBGA680
封裝： PLASTIC, FBGA-680
文件頁(yè)數(shù)： 24/94頁(yè)
文件大?。?/td> 2104K
代理商： M-ORT82G51BM680-DB
Lattice Semiconductor
ORCA ORT82G5 Data Sheet
30
XAUISTAT_xx - In XAUI mode, they should be 10.
Monitor the following status bits in registers 30805, 30905
DEMUXWAS_xx-They should be 1 indicating word alignment is achieved.
CH248_SYNCxx-They should be 1 indicating channel alignment. This is cleared by resync.
4.
Write a 1 to the appropriate resync registers 30820, 30920. Note that this assumes that the previous value of
the resync bits are 0. The resync operation requires a rising edge. Two writes are required to the resync bits:
write a 0 and then write a 1.
Check out-of-sync and FIFO overow status in registers 30814 (Bank A).
SYNC4_A_OOS, SYNC4_A_OVFL-by 4 alignment.
SYNC2_A2_OOS, SYNC_A2_OVFL or SYNC2_A1_OOS, SYNC2_A1_OVFL-by 2 alignment.
Check out-of-sync status in registers 30914 (Bank B).
SYNC4_B_OOS, SYNC4_B_OVFL-by 4 alignment.
SYNC_B2_OOS, SYNC2_B2_OVFL or SYNC2_B1_OOS, SYNC_B1_OVFL-by 2 alignment.
Check out-of-sync status in register 30A03
SYNC8_OOS, SYNC8_OVFL-by 8 alignment.
If out-of-sync bit is 1, then rewrite a 1 to the appropriate resync registers and monitor the OOS bit again. If Out of
Synchronization (OOS) bit is 0 but OVFL bit is 1, then check if the RX_FIFO_MIN value has been programmed to
a value > 0. (Default value is 0.) Change the value to 0 and check the OVFL bit again. If OOS and OVFL are 1,
then rewrite a 1 to the appropriate resync registers. The resync operation requires a rising edge. Two writes are
required to the resync bits: write a 0 and then write a 1.
Embedded Core/FPGA Interface
This block provides the data formatting and receive data and clock signal transfers between the Embedded Core
and the FPGA Logic. There are also control and status registers in the FPGA portion of the chip which contain bits
to control the receive logic and to record status. These are described in later sections of this data sheet, Table 8,
and communicate with the core using the System Bus.
The demultiplexed, receive word outputs to the FPGA are shown in Figure 6. . These are each 40 bits wide. There
are eight of these interfaces, one for each SERDES channel. Each consist of four groups of 10-bit data or four
groups of decoded information depending on setting of 8b10bR_xx control register bits.
Each 10-bit group of decoded information includes 8 bits of data and a 1 bit K_CTRL indicator derived from the
received data and a tenth bit of status information. The function of the tenth bit varies from group to group and
includes code violation, Out of Synchronization (OOS) indicators and the CH248_SYNC_xx status bit.
CH248_SYNC_xx indicates the status of multi-channel alignment of channel xx and is high when the count for the
multi-channel alignment block reaches zero regardless of whether or not multi-channel alignment is successful.
The mapping of the 10-bit groups to the MRWD_xx[39:0] bits output to the FPGA logic is summarized in Table 5
and Table . The various functions of the bits that vary from channel to channel, i.e., bits 29 and 19, are also
described in Table .]
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