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參數(shù)資料
| 型號(hào)： | LV24010LP |
| 元件分類(lèi)： | 調(diào)諧器 |
| 英文描述： | 1-BAND, AUDIO TUNER, QCC40 |
| 封裝： | 5 X 5 MM, VQLP-40 |
| 文件頁(yè)數(shù)： | 2/18頁(yè) |
| 文件大小： | 445K |
| 代理商： | LV24010LP |
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LV24010LP
No.A0466-10/18
Block 1, Register 08h - IRQ_MSK - Interrupt Mask Register (Write-only)
7
6
5
4
3
2
1
0
Reserved
IM_MS
Reserved
IRQ_LVL
IM_AFC
IM_FS
IM_CNT2
bit 7:
Reserved:
Must be programmed with 0.
bit 6:
IM_MS:
Mono/Stereo interrupt mask bit.
0 = Disable mono/stereo change interrupt.
1 = Enable mono/stereo change interrupt.
bit 5:
Reserved:
Must be programmed with 0.
bit 4:
Reserved:
Must be programmed with 0.
bit 3:
IRQ_LVL:
Interrupt level select bit.
0 = Drive DATA-line from low to high when interrupt occurs (active high).
1 = Drive DATA-line from high to low when interrupt occurs (active low).
bit 2:
IM_AFC:
AFC out of range interrupt mask bit.
0 = Disable AFC out of range interrupt.
1 = Enable AFC out of range interrupt.
bit 1:
IM_FS:
Field strength change interrupt mask bit.
0 = Disable field strength change interrupt.
1 = Enable field strength change interrupt.
bit 0:
IM_CNT2:
Counter 2 counting done interrupt mask bit.
0 = Disable counter 2 counting done interrupt.
1 = Enable counter 2 counting done interrupt.
Block 1, Register 09h - FM_CAP - FM RF Capacitor Bank Register (Write-only)
7
6
5
4
3
2
1
0
FMCAP[7:0]
bit 7-0:
FMCAP[7:0]:
CAP bank value to control the FM RF frequency (coarse steps)
Note:
- 7 bit CAP value (Bit[7:6]: Combination 10b and 01b results in the same CAP-range).
- Negative control: de RF frequency decreases when increasing the register’s value.
- See also FM_OSC register.
Block 1, Register 0Ah - CNT_L - Counter Value Low Register (Read-only)
7
6
5
4
3
2
1
0
CNT_LSB[7:0]
bit 7-0:
CNT_LSB[7:0]:
Lower 8-bit value of the 16 bit counter
Block 1, Register 0Bh - CNT_H - Counter Value High Register (Read-only)
7
6
5
4
3
2
1
0
CNT_MSB[7:0]
bit 7-0:
CNT_MSB[7:0]:
Upper 8-bit value of the 16 bit counter
Block 1, Register 0Ch - CTRL_STAT - Control Status Register (Read-only)
7
6
5
4
3
2
1
0
REV3
REV2
REV1
REV0
Reserved
COV_FLG
AFC_FLG
bit 7-4:
REV[3:0]:
should be read as 0Dh.
bit 3-1:
Reserved[1:0]:
should be read as all 1
bit 1:
COV_FLG:
counter overflow flag.
0 = No overflow of the internal counter.
1 = The last counting loop causes overflow of the internal counter.
bit 0:
AFC_FLG:
AFC out of range bit
0 = AFC is within control range.
1 = AFC is out of control range.
Note:
- Reading this register will clear AFC, count 2 done interrupt.
- COV_FLG is clear when CLR_CNT1 bit of CNT_CTRL register is high.
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