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參數(shù)資料
| 型號： | LV23401V |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO30 |
| 封裝： | 0.275 INCH, SSOP-30 |
| 文件頁數(shù)： | 7/24頁 |
| 文件大?。?/td> | 594K |
| 代理商： | LV23401V |
LV23401V
No.A1746-15/24
Register 0Fh – AMCTRL – AM Station Control (Read/Write)
7
6
5
4
3
2
1
0
AMDIV[2:0]
AM_CAL
ACAP11
ACAP10
ACAP9
ACAP8
Bit 7 – 5 :
AMDIV[2:0] : AM Clock Divider
Bit 7 :
AM_CD2 : AM Clock Divider bit 2.
Bit 6 :
AM_CD1 : AM Clock Divider bit 1.
Bit 5 :
AM_CD0 : AM Clock Divider bit 0.
Note : AMCD[2:0] uses the frequency of FM belt even for the AM belt to lower.
Set the machine of the AM dividing frequency to turning off at FM mode.
AM_CD[2:0]
Rate of dividing frequency
Rough estimate AM-RF frequency (In kHz)
0,1
Divider OFF
0 (FM mode)
2
224
338 – 483
3
160
474 – 676
4
112
676 – 966
5
80
947 – 1353
6
64
1183 – 1692
7
48
1578 - 2256
Bit 4 :
NA ( 0 Fixation)
Bit 3 – 0 :
AMCAP[11:8] : AM antenna capacitor bank.
Bit 3 :
AMCAP_bit11
Bit 2 :
AMCAP_bit10
Bit 1 :
AMCAP_bit9
Bit 0 :
AMCAP_bit8
Register 10h – DO_REF_CLK_CNF – Do output mode and reference clock configuration (Read/Write)
7
6
5
4
3
2
1
0
IPOL
DO_SEL[1:0]
EXT_CLK_CFG[1:0]
FS_S[2:0]
Bit 7 :
IPOL : Indicator (DO pin _SD/ST mode) polarity
0 = SD/ST Active Low (The same state change as 13pin – SD pin / 14pin – ST pin )
1 = SD/ST Active High (State change opposite to 13pin – SD pin / 14pin – ST pin )
Note : This bit doesn't influence the polarity of the serial data.
Bit 6 -5 :
DO_SEL : DO pin select (DO pin output mode select)
DO_SEL[1:0]
DO pin
00
Serial data output mode
01
ST pin mode
10
SD pin mode
11
Local position confirmation mode
DO pin is used by observing the position (Upper heterodyne / Lower heterodyne) of a state of SD pin/ST pin besides the serial data output and local
OSC.
* The state of DO pin changes synchronizing with SD pin / ST pin when DO_SEL is set to (01b) or (10b).
* The state of DO pin changes by the position of Local OSC when DO is set to (11b). Lower heterodyne = 0, Upper heterodyne = 1
* Set DO_SEL to (00b) when you output the serial data.
Bit 4 – 3 :
EXT_CLK_CFG[1:0] : External clock setting
EXT_CLK_CFG[1:0]
Reference clock
00
Off
01
The external clock is supplied.
10
32768Hz Crystal oscillation
11
Unused
Bit 2 – 0 :
FS_S[2:0] : SD(Station Detector) operate level setting (distinguishes at the FS level )
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| LV23401V_11 | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:For Home Stereo System 1-chip Tuner IC Incorporating PLL |
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| LV23401V-N-MPB-H | 制造商:ON Semiconductor 功能描述:AM/FM 1CHIP HOME TUNER - Ammo Pack 制造商:ON Semiconductor 功能描述:FNFLD / AM/FM 1CHIP HOME TUNER |
| LV23401V-N-TLM-H | 功能描述:調(diào)諧器 RoHS:否 制造商:NXP Semiconductors 功能: 噪聲系數(shù): 工作電源電壓: 最小工作溫度: 最大工作溫度: |
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