參數(shù)資料
型號: LPC11U14FHN33/201,
廠商: NXP Semiconductors
文件頁數(shù): 31/72頁
文件大?。?/td> 0K
描述: IC MCU 32BIT 32K 33HVQFN
產品培訓模塊: Code Density for LPC11xx
標準包裝: 260
系列: LPC11Uxx
核心處理器: ARM? Cortex?-M0
芯體尺寸: 32-位
速度: 50MHz
連通性: I²C,Microwire,智能卡,SPI,SSP,UART/USART,USB
外圍設備: 欠壓檢測/復位,POR,WDT
輸入/輸出數(shù): 26
程序存儲器容量: 32KB(32K x 8)
程序存儲器類型: 閃存
RAM 容量: 6K x 8
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 3.6 V
數(shù)據(jù)轉換器: A/D 8x10b
振蕩器型: 內部
工作溫度: -40°C ~ 85°C
封裝/外殼: 32-VQFN 裸露焊盤
包裝: 托盤
其它名稱: 568-8581
LPC11U1X
All information provided in this document is subject to legal disclaimers.
NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 2.2 — 11 March 2014
37 of 72
NXP Semiconductors
LPC11U1x
32-bit ARM Cortex-M0 microcontroller
9.1 BOD static characteristics
[1]
Interrupt levels are selected by writing the level value to the BOD control register BODCTRL, see
LPC11U1x user manual.
9.2 Power consumption
Power measurements in Active, Sleep, and Deep-sleep modes were performed under the
following conditions (see LPC11U1x user manual):
Configure all pins as GPIO with pull-up resistor disabled in the IOCON block.
Configure GPIO pins as outputs using the GPIOnDIR registers.
Write 0 to all GPIOnDATA registers to drive the outputs LOW.
Table 8.
BOD static characteristics[1]
Tamb =25 C.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Vth
threshold voltage
interrupt level 1
assertion
-
2.22
-
V
de-assertion
-
2.35
-
V
interrupt level 2
assertion
-
2.52
-
V
de-assertion
-
2.66
-
V
interrupt level 3
assertion
-
2.80
-
V
de-assertion
-
2.90
-
V
reset level 0
assertion
-
1.46
-
V
de-assertion
-
1.63
-
V
reset level 1
assertion
-
2.06
-
V
de-assertion
-
2.15
-
V
reset level 2
assertion
-
2.35
-
V
de-assertion
-
2.43
-
V
reset level 3
assertion
-
2.63
-
V
de-assertion
-
2.71
-
V
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