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| 型號： | LPC11U14FHN33/201, |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 13/72頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 32BIT 32K 33HVQFN |
| 產(chǎn)品培訓模塊： | Code Density for LPC11xx |
| 標準包裝： | 260 |
| 系列： | LPC11Uxx |
| 核心處理器： | ARM? Cortex?-M0 |
| 芯體尺寸： | 32-位 |
| 速度： | 50MHz |
| 連通性： | I²C，Microwire，智能卡，SPI，SSP，UART/USART，USB |
| 外圍設(shè)備： | 欠壓檢測/復(fù)位，POR，WDT |
| 輸入/輸出數(shù)： | 26 |
| 程序存儲器容量： | 32KB（32K x 8） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 6K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 1.8 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 32-VQFN 裸露焊盤 |
| 包裝： | 托盤 |
| 其它名稱： | 568-8581 |
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LPC11U1X
All information provided in this document is subject to legal disclaimers.
NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 2.2 — 11 March 2014
20 of 72
NXP Semiconductors
LPC11U1x
32-bit ARM Cortex-M0 microcontroller
The USART uses a fractional baud rate generator. Standard baud rates such as
115200 Bd can be achieved with any crystal frequency above 2 MHz.
7.9.1 Features
Maximum USART data bit rate of 3.125 Mbit/s.
16-byte receive and transmit FIFOs.
Register locations conform to 16C550 industry standard.
Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.
Built-in fractional baud rate generator covering wide range of baud rates without a
need for external crystals of particular values.
Fractional divider for baud rate control, auto baud capabilities and FIFO control
mechanism that enables software flow control implementation.
Support for RS-485/9-bit mode.
Support for modem control.
Support for synchronous mode.
Includes smart card interface.
7.10 SSP serial I/O controller
The SSP controllers are capable of operation on a SSP, 4-wire SSI, or Microwire bus. It
can interact with multiple masters and slaves on the bus. Only a single master and a
single slave can communicate on the bus during a given data transfer. The SSP supports
full duplex transfers, with frames of 4 bits to 16 bits of data flowing from the master to the
slave and from the slave to the master. In practice, often only one of these data flows
carries meaningful data.
7.10.1 Features
Maximum SSP speed of 25 Mbit/s (master) or 4.17 Mbit/s (slave) (in SSP mode)
Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National
Semiconductor Microwire buses
Synchronous serial communication
Master or slave operation
8-frame FIFOs for both transmit and receive
4-bit to 16-bit frame
7.11 I2C-bus serial I/O controller
The LPC11U1x contain one I2C-bus controller.
The I2C-bus is bidirectional for inter-IC control using only two wires: a Serial Clock line
(SCL) and a Serial Data line (SDA). Each device is recognized by a unique address and
can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the
capability to both receive and send information (such as memory). Transmitters and/or
receivers can operate in either master or slave mode, depending on whether the chip has
to initiate a data transfer or is only addressed. The I2C is a multi-master bus and can be
controlled by more than one bus master connected to it.
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