System-on-Chip
LH79524/LH79525
Preliminary data sheet
Rev. 01
—
16 July 2007
7
NXP Semiconductors
M3
PB7/INT1/UARTTX0/
UARTIRTX0
PC0/A16
PC1/A17
PC2/A18
PC3/A19
PC4/A20
PC5/A21
I/O
General Purpose I/O Signal — Port B7; multiplexed with UART0 Infrared Transmit-
ted Serial Data Output, UART0 Serial Transmit Data Out, and External Interrupt 1.
General Purpose I/O Signal — Port C0; multiplexed with Address A16
General Purpose I/O Signal — Port C1; multiplexed with Address A17
General Purpose I/O Signal — Port C2; multiplexed with Address A18
General Purpose I/O Signal — Port C3; multiplexed with Address A19
General Purpose I/O Signal — Port C4; multiplexed with Address A20
General Purpose I/O Signal — Port C5; multiplexed with Address A21
General Purpose I/O Signal — Port C6; multiplexed with Address A22 and NAND
Flash Write Enable
General Purpose I/O Signal — Port C7; multiplexed with Address A23 and NAND
Flash Read Enable
General Purpose I/O Signal — Port D0; multiplexed with Data D8
General Purpose I/O Signal — Port D1; multiplexed with Data D9
General Purpose I/O Signal — Port D2; multiplexed with Data D10
General Purpose I/O Signal — Port D3; multiplexed with Data D11
General Purpose I/O Signal — Port D4; multiplexed with Data D12
General Purpose I/O Signal — Port D5; multiplexed with Data D13
General Purpose I/O Signal — Port D6; multiplexed with Data D14
N7
R6
T5
P6
R5
T4
I/O
I/O
I/O
I/O
I/O
I/O
P5
PC6/A22/nFWE
I/O
R4
PC7/A23/nFRE
I/O
P15
P14
N13
T15
N12
T14
P12
PD0/D8
PD1/D9
PD2/D10
PD3/D11
PD4/D12
PD5/D13
PD6/D14
I/O
I/O
I/O
I/O
I/O
I/O
I/O
T13
PD7/D15
I/O
General Purpose I/O Signal — Port D7; multiplexed with Data D15
General Purpose I/O Signals — Port E0; multiplexed with LCD Line Pulse and
AD-TFT/HR-TFT Line Pulse
General Purpose I/O Signals — Port E1; multiplexed with LCD Data Clock
General Purpose I/O Signals — Port E2; multiplexed with LCD Power Save
General Purpose I/O Signals — Port E3; multiplexed with LCD Row Driver Clock
General Purpose I/O Signals — Port E4; multiplexed with LCD Panel Power
Enable and LCD Reverse
General Purpose I/O Signals — Port E5; multiplexed with LCD VDD Enable
General Purpose I/O Signals — Port E6; multiplexed with LCD Analog Power
Enable and MOD
General Purpose I/O Signals — Port E7; multiplexed with nWAIT and DMA End of
Transfer
General Purpose I/O Signals — Port F0; multiplexed with LCD Video Data bit 6
General Purpose I/O Signals — Port F1; multiplexed with LCD Video Data bit 7
General Purpose I/O Signals — Port F2; multiplexed with LCD Video Data bit 8
General Purpose I/O Signals — Port F3; multiplexed with LCD Video Data bit 9
General Purpose I/O Signals — Port F4; multiplexed with LCD Video Data bit 10
General Purpose I/O Signals — Port F5; multiplexed with LCD Video Data bit 11
General Purpose I/O Signals — Port F6; multiplexed with LCD Start Pulse Left
General Purpose I/O Signals — Port F7; multiplexed with LCD Row Driver
Counter reset
General Purpose I/O Signals — Port G0; multiplexed with Ethernet TX Enable
General Purpose I/O Signals — Port G1; multiplexed with Ethernet TX Clock
General Purpose I/O Signals — Port G2; multiplexed with LCD Video Data bit 0
General Purpose I/O Signals — Port G3; multiplexed with LCD Video Data bit 1
General Purpose I/O Signals — Port G4; multiplexed with LCD Video Data bit 2
B12
PE0/LCDLP/
LCDHRLP
PE1/LCDDCLK
PE2/LCDPS
PE3/LCDCLS
PE4/LCDDSPLEN/
LCDREV
PE5/LCDVDDEN
PE6/LCDVEEN/
LCDMOD
I/O
D11
B13
C13
I/O
I/O
I/O
D12
I/O
B16
I/O
B15
I/O
D14
PE7/nWAIT/nDEOT
I/O
A8
A9
B9
C9
B10
A11
B11
PF0/LCDVD6
PF1/LCDVD7
PF2/LCDVD8
PF3/LCDVD9
PF4/LCDVD10
PF5/LCDVD11
PF6/LCDEN/LCDSPL
I/O
I/O
I/O
I/O
I/O
I/O
I/O
A12
PF7/LCDFP/LCDSPS
I/O
A5
B6
A6
C7
B7
PG0/ETHERTXEN
PG1/ETHERTXCLK
PG2/LCDVD0
PG3/LCDVD1
PG4/LCDVD2
I/O
I/O
I/O
I/O
I/O
Table 2. LH79524 Pin Descriptions (Cont’d)
LFBGA
PIN
SIGNAL NAME
TYPE
DESCRIPTION