參數(shù)資料
型號(hào): LH79525N0Q100A1
廠商: NXP Semiconductors N.V.
元件分類: 數(shù)學(xué)處理器
英文描述: System-on-Chip
封裝: LH79524N0F100A1<SOT1019-1 (LFBGA208)|<<http://www.nxp.com/packages/SOT1019-1.html<1<Always Pb-free,;LH79525N0Q100A1<SOT1017-1 (LQFP176)|<<http://www.nxp.com/packages/SOT1
文件頁數(shù): 51/64頁
文件大小: 970K
代理商: LH79525N0Q100A1
System-on-Chip
LH79524/LH79525
Preliminary data sheet
Rev. 01
16 July 2007
51
NXP Semiconductors
Figure 32. AD-TFT, HR-TFT Horizontal Timing
Figure 33. AD-TFT, HR-TFT Vertical Timing
1 AD-TFT or HR-TFT HORIZONTAL LINE
AD-TFT and HR-TFT SIGNALS ARE TFT SIGNALS, RE-TIMED
TIMING0:HSW
TIMING0:HSW +
TIMING0: HBP
PIXEL DATA
1 LCDDCLK
002 003 004 005 006
318
317
319 320
001
1 LCDDCLK
ALITIMING1:LPDEL
ALITIMING1:PSCLS
ALITIMING2:PS2CLS2
ALITIMING2:SPLDEL
002 003 004 005 006 007 008
320
001
*
CLCDCLK
(INTERNAL)
APBPERIPHCLKCTRL1:LCD
CLKPRESCALE:LCDPS
(SHOWN FOR REFERENCE)
LCDLP
(HORIZONTAL
SYNCHRONIZATION
PULSE)
I
A
O
A
LCDDCLK
(PANEL CLOCK)
TIMING2:PCD
TIMING2:BCD
TIMING2:IPC
TIMING2:CPL
LCDVD[11:0] (LH79525)
LCDVD[15:0] (LH79524)
16 × (TIMING0:PPL+1)
LCDDCLK
(DELAYED FOR
AD-TFT, HR-TFT)
LCDVD[11:0] (LH79525)
LCDVD[15:0] (LH79524)
(DELAYED FOR
AD-TFT, HR-TFT)
LCDSPL
(AD-TFT, HR-TFT
START PULSE LEFT)
LCDLP
(HORIZONTAL
SYNCHRONIZATION
PULSE)
LCDCLS
LCDPS
LCDREV
LCDEN
(INTERNAL DATA ENABLE)
LH79525-42
NOTE:
*
Source is RCPC.
LCDSPS
(VERTICAL
SYNCHRONIZATION)
LCDLP
(HORIZONTAL
SYNCHRONIZATION
PULSE)
LCDVD[11:0]
(LCD VIDEO DATA)
NOTE
: LCDDCLK can range from 4.5 MHz to 6.8 MHz.
LH79525-43
TIMING1:VSW
1.5 μs - 4 μs
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