- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄299403 > LFSCM3GA80EP1-6FCN1704C (LATTICE SEMICONDUCTOR CORP) PDF資料下載
參數(shù)資料
| 型號： | LFSCM3GA80EP1-6FCN1704C |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | FPGA |
| 中文描述： | FPGA, 308 CLBS, 80000 GATES, 1000 MHz, CBGA1704 |
| 封裝： | 42.5 X 42.5 MM, LEAD FREE, CERAMIC, FCBGA-1704 |
| 文件頁數(shù)： | 175/243頁 |
| 文件大?。?/td> | 2674K |
| 代理商： | LFSCM3GA80EP1-6FCN1704C |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁當(dāng)前第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁第193頁第194頁第195頁第196頁第197頁第198頁第199頁第200頁第201頁第202頁第203頁第204頁第205頁第206頁第207頁第208頁第209頁第210頁第211頁第212頁第213頁第214頁第215頁第216頁第217頁第218頁第219頁第220頁第221頁第222頁第223頁第224頁第225頁第226頁第227頁第228頁第229頁第230頁第231頁第232頁第233頁第234頁第235頁第236頁第237頁第238頁第239頁第240頁第241頁第242頁第243頁
2-33
Architecture
Lattice Semiconductor
LatticeSC/M Family Data Sheet
this allows for easy integration with the rest of the system. These capabilities make the LatticeSC ideal for many
multiple power supply and hot-swap applications. The maximum current during hot socketing is 4mA. See Hot
Socketing Specifications in Chapter 3 of this data sheet.
Power-Up Requirements
To prevent high power supply and input pin currents, each VCC, VCC12, VCCAUX, VCCIO and VCCJ power sup-
plies must have a monotonic ramp up time of 75 ms or less to reach its minimum operating voltage. Apart from
VCC and VCC12, which have an additional requirement, and VCCIO and VCCAUX, which also have an additional
requirement, the VCC, VCC12, VCCAUX, VCCIO and VCCJ power supplies can ramp up in any order, with no
restriction on the time between them. However, the ramp time for each must be 75 ms or less. Configuration of the
device will not proceed until the last power supply has reached its minimum operating voltage.
Additional Requirement for VCC and VCC12:
VCC12 must always be higher than VCC. This condition must be maintained at ALL times, including during power-
up and power-down. Note that for 1.2V only operation, it is advisable to source both of these supplies from the
same power supply.
Additional Requirement for VCCIO and VCCAUX:
If any VCCIOs are 1.2/1.5/1.8V, then VCCAUX MUST be applied before them. If any VCCIO is 1.2/1.5/1.8V and is
powered up before VCCAUX, then when VCCAUX is powered up, it may drag VCCIO up with it as it crosses
through the VCCIO value. (Note: If the VCCIO supply is capable of sinking current, as well as the more usual
sourcing capability, this behavior is eliminated. However, the amount of current that the supply needs to sink is
unknown and is likely to be in the hundreds of milliamps range).
Power-Down Requirements
To prevent high power supply and input pin currents, power must be removed monotonically from either VCC or
VCCAUX (and must reach the power-down trip point of 0.5V for VCC, 0.95V for VCCAUX) before power is removed
monotonically from VCC12, any of the VCCIOs, or VCCJ. Note that VCC12 can be removed at the same time as
VCC, but it cannot be removed earlier. In many applications, VCC and VCC12 will be sourced from the same power
supply and so will be removed together. For systems where disturbance of the user pins is a don't care condition,
the power supplies can be removed in any order as long as they power down monotonically within 200ms of each
other.
Additionally, if any banks have VCCIO=3.3V nominal (potentially banks 1, 4, 5) then VCCIO for those banks must
not be lower than VCCAUX during power-down. The normal variation in ramp-up times of power supplies and volt-
age regulators is not a concern here.
Note: The SERDES power supplies are NOT included in these requirements and have no specific sequencing
requirements. However, when using the SERDES with VDDIB or VDDOB that is greater than 1.2V (1.5V nominal
for example), the SERDES should not be left in a steady state condition with the 1.5V power applied and the 1.2V
power not applied. Both the 1.2V and 1.5V power should be applied to the SERDES at nominally the same time.
The normal variation in the ramp-up times of power supplies and voltage regulators is not a concern here.
SERDES Power Supply Sequencing Requirements
When using the SERDES with 1.5V VDDIB or VDDOB supplies, the SERDES should not be left in a steady state
condition with the 1.5V power applied and the 1.2V power not applied. Both the 1.2V and the 1.5V power should be
applied to the SERDES at nominally the same time. The normal variation in ramp-up times of power supples and
voltage regulators is not a concern.
Additional Requirement for SERDES Power Supply
All VCC12 pins need to be connected on all devices independent of functionality used on the device. This analog
supply is used by both the RX and TX portions of the SERDES and is used to control the core SERDES logic
regardless of the SERDES being used in the design. VDDIB and VDDOB are used as supplies for the terminations
on the CML input and output buffers. If a particular channel is not used, these can be UNCONNECTED (floating).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LFSC3GA15E-6FN256I | |
| LFSCM3GA40EP1-5FFN1020I | |
| LFXP2-40E-6FN484I | |
| LFXP2-17E-7F484C | |
| LFXP20E-3FN484C | |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LFSCM3GA80EP1-6FCN1704I | 功能描述:FPGA - 現(xiàn)場可編程門陣列 80.1K LUTs 904 I/O MACOSERDES 1.2V -6I RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| LFSCM3GA80EP1-6FF1152C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 80.1K LUTs 660 I/O MACO SERDES1.2V -6SP RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| LFSCM3GA80EP1-6FF1152I | 功能描述:FPGA - 現(xiàn)場可編程門陣列 80.1K LUTs 660 I/O MACO SERDES1.2V -6SP RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| LFSCM3GA80EP1-6FF1704C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 80.1K LUTs 904 I/O MACO SERDES1.2V -6SP RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| LFSCM3GA80EP1-6FF1704I | 功能描述:FPGA - 現(xiàn)場可編程門陣列 80.1K LUTs 904 I/O MACO SERDES1.2V -6SP RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。