參數(shù)資料
型號(hào)： LC72144M
廠(chǎng)商： SANYO SEMICONDUCTOR CO LTD
元件分類(lèi)： PLL合成/DDS/VCOs
英文描述： PLL FREQUENCY SYNTHESIZER, 40 MHz, PDSO24
封裝： MFP-24
文件頁(yè)數(shù)： 7/22頁(yè)
文件大?。?/td> 307K
代理商： LC72144M
Programmable Divider
Note: ! = don’t care
General-Purpose Counter
The LC72144M includes a general-purpose 20-bit binary counter whose value can be read out from the DO pin, MSB
first.
When using this counter for frequency measurement, one of four measurement times (4, 8, 32, or 64 ms) is selected by
GT0 and GT1. The frequency input to either the HCTR or the LCTR pin can be measured by determining the number of
pulses input to the counter during the measurement period.
This counter can be used to measure the period of the signal input to the LCTR pin by determining how many cycles of a
reference signal (900 kHz) are input to the counter during one or two periods of the LCTR pin signal.
No. 5377-15/22
LC72144M
DVS
SNS
Divisor setting (N)
Input frequency range
Input port
(A)
1
!
272 to 65535
10 to 160 MHz
FMIN
(B)
0
1
272 to 65535
2 to 40 MHz
AMIN
(C)
0
4 to 4095
0.5 to 10 MHz
AMIN
Minimum input sensitivity (f [MHz])
(A) FMIN
10
≤ f< 130
130
≤ f < 160
40 mVrms
70 mVrms
(B) AMIN
2
≤ f < 25
25
≤ f < 40
40 mVrms
70 mVrms
(C) AMIN
0.5
≤ f < 2.5
2.5
≤ f < 10
40 mVrms
70 mVrms
One period/two
periods extraction
Check signal: 900 kHz
Input signal
switching gate
General-purpose counter
(20-bit binary counter)
DO pin
C = FIF
× GT
C = (1/T) ÷ check signal (900 kHz)
0 to 3
4 to 7 8 to 11 12 to 15 16 to 19
相關(guān)PDF資料
PDF描述
LC72151V PLL FREQUENCY SYNTHESIZER, 40 MHz, PDSO30
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