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參數(shù)資料
| 型號： | LC72144M |
| 廠商： | SANYO SEMICONDUCTOR CO LTD |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 40 MHz, PDSO24 |
| 封裝： | MFP-24 |
| 文件頁數(shù)： | 6/22頁 |
| 文件大小： | 307K |
| 代理商： | LC72144M |
Structure of the DO Output Data (Serial Data Output)
3. OUT
No. 5377-14/22
LC72144M
No.
Control section/
Function
Related data
data
I/O port data
I0 to I7
General-
purpose
counter binary
data
C0 to C19
A/D converter
ADC0 data
AD00 to AD05
A/D converter
data
ADC1 data
AD10 to AD15
(1)
(2)
(3)
(4)
I/O-0 to I/O-5,
H/I-6, L/I-7
CTS0, CTS1, CTE
ADI0, ADI1, ADS
I/O port data: The I0 to I7 pins reflect the latched I/O-0 to I/O-7 I/O port pin states. Data is latched
when data output mode is entered.
The pin states are latched regardless of the input or output mode specification.
Pin state = high: 1, low: 0
Counter contents
Bits C0 to C19 are the latched contents of the 20-bit binary counter. C0 is the LSB.
C19: MSB
C0: LSB
The result of A/D conversion of the signal input to the ADC0 pin is latched and output from the AD00 to
AD05 pins
AD05: MSB
AD00: LSB
The result of A/D conversion of the signal input to the ADC1 pin is latched and output from the AD10 to
AD15 pins
AD15: MSB
AD10: LSB
Address
Data with a value of 0.
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