- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄3980 > KXPC8240LVV200E (Freescale Semiconductor)IC MPU INTEGRATED 250MHZ 352TBGA PDF資料下載
參數(shù)資料
| 型號： | KXPC8240LVV200E |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 41/52頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU INTEGRATED 250MHZ 352TBGA |
| 標準包裝： | 2 |
| 系列： | MPC82xx |
| 處理器類型： | 32-位 MPC82xx PowerQUICC II |
| 速度： | 200MHz |
| 電壓： | 2.5V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 352-LBGA |
| 供應(yīng)商設(shè)備封裝： | 352-TBGA（35x35） |
| 包裝： | 托盤 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁當(dāng)前第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁
46
MPC8240 Integrated Processor Hardware Specifications
Document Revision History
0.3
Removed “PowerPC Platform compliant” from first sentence on cover sheet.
Changed PCI 2.1—’compatible’ to ‘compliant’ in Section 1.2.
Updated Table 5 and its notes with preliminary power-consumption information.
Updated Table 6, removing 266 MHz frequency information.
Made corrections to Table 7.
Items 5a and 5b were changed to correct values for 66-MHz PCI_SYNC_IN.
OSC_IN Frequency Stability spec from 1000 to 100 ppm.
Table 9:
Changed item 12b1 from 8.0 to 7.0 ns.
Added item 12b3, Output Valid for ROM accesses.
Table 11, item 2, “KAHLUA” terminology replaced with MPC8240.
Added EPIC Serial Interrupt Timing Section with two new figures, causing cross-references to
subsequent figures to be updated.
Updated formatting of pin out in Table 17.
Modified notes section in Table 17:
Split Note 3 into new Notes 3 and 12. Notes 3, 5, and 7 cover internal pull-up resistors active only
during the reset state. Note 12 covers internal pull-up resistors enabled at all times.
Note 11 has been revised.
Added Note 10 to SDA and SCL signals for consistency with theMPC8240 User’s Manual.
Added Note 10 to SMI and TBEN; inputs that should have pull-ups and for consistency with reference
designs.
Added Note 10 to SRESET and CHKSTOP_IN for consistency with Figure 23 (COP Connector)
Added Notes 13 and 14 for output valid specifications dependent upon memory mode.
Added Note 15 for pins affected by programmable PCI output valid and hold time.
Added Notes 16 –18 relating to open drain pins.
Figure 18:
Revised 200-MHz column to reflect PCI_SYNC_IN 66-MHz upper limit.
Refs 1E and 1F not usable entries made to match others in the table.
Revised Notes 4 and 5 changing OSC_IN to PCI_SYNC_IN.
Removed 266-MHz column.
Removed Ref 0x06 for dual PLL bypass mode; added it to reserved list in Note 3.
Revised Note 4 describing PLL bypass mode.
Added missing cross-reference in Section 1.7.2 and corrected Schottky reference to the 1N5820 diodes.
Added Section 1.7.2 on power supply sizing.
Modified internal pull-up resistor list in Section 1.7.5 to be consistent with Notes of Table 17; added reset
configuration pin pull-down resistor value recommendation.
Modified Figure 23, COP connector diagram:
Reversed direction of CKSTP_IN arrow to show it going in.
Added a pull-up resistor on TRST.
Changed R-spec device’s VDD range from 2.5–2.625 V to 2.5–2.75 V.
0.4
Modified DLL Lock Range with DLL_EXTEND = 1 equation in Table 7 from 0
≤ (NT
clk/2 – tloop – tfix0) ≤ 7
to 0
≤(NT
clk – Tclk/2 – tloop – tfix0) ≤ 7.
Modified Figure 5 to only show Tloop up to 15 ns, not practical to implement Tloop beyond 15 ns.
Modified DL[0:31] and DH[0:31] signal names to MDL[0:31] and MDH[0:31], respectively, in Table 17 to
be consistent with the Tundra Tsi107 PowerPC host bridge data bus naming convention.
Several active low signal names in Table 17 inadvertently had the overline formatting removed during the
final edit process of the previous revision. The signals are shown correctly with overlines in this version.
Signals affected were: DEVSEL, FRAME, LOCK, PERR, SERR, STOP, TRDY, INTA, FOE, RCS0, RCS1,
SDRAS, SDCAS, WE, AS, HRST_CTRL, HRST_CPU, MCP, SMI, SRESET, CHKSTOP_IN, and MIV.
Table 19. Document Revision History (continued)
Revision
Number
Substantive Change(s)
F
re
e
sc
a
le
S
e
m
ic
o
n
d
u
c
to
r,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
c
..
.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AMM43DREF | CONN EDGECARD 86POS .156 EYELET |
| IDT70V657S15BF | IC SRAM 1.125MBIT 15NS 208FBGA |
| KXPC823VR81B2T | IC MPU POWERQUICC 81MHZ 256-PBGA |
| HMM44DREN | CONN EDGECARD 88POS .156 EYELET |
| KMPC880VR80 | IC MPU POWERQUICC 80MHZ 357PBGA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| KXPC8240LZU200E | 制造商:Freescale Semiconductor 功能描述: |
| KXPC8240RVV250E | 功能描述:IC MPU INTEGRATED 250MHZ 352TBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:MPC82xx 標準包裝:1 系列:MPC85xx 處理器類型:32-位 MPC85xx PowerQUICC III 特點:- 速度:1.2GHz 電壓:1.1V 安裝類型:表面貼裝 封裝/外殼:783-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:783-FCPBGA（29x29） 包裝:托盤 |
| KXPC8250AZUPHBA | 制造商:Motorola Inc 功能描述: |
| KXPC8255CVVIFBC | 功能描述:微處理器 - MPU PQ 2 HIP 3 NO-PB RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| KXPC8255CZUIFBC | 功能描述:微處理器 - MPU POWERQUICC II HIP3 REV C RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。