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參數(shù)資料
| 型號(hào)： | KM48S8020B |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 4M x 8Bit x 2 Banks Synchronous DRAM(4M x 8位 x 2組同步動(dòng)態(tài)RAM) |
| 中文描述： | 4米× 8位× 2銀行同步DRAM（4米× 8位× 2組同步動(dòng)態(tài)RAM）的 |
| 文件頁數(shù)： | 5/43頁 |
| 文件大?。?/td> | 604K |
| 代理商： | KM48S8020B |
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KM48S8020B
CMOS SDRAM
REV .7 July 1998
1. Measured with outputs open.
2. Refresh period is 64ms.
3. KM48S8020BT-G**
4. KM48S8020BT-F**
Notes :
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, T
A
= 0 to 70
°
C)
Parameter
Symbol
Test Condition
CAS
Latency
Version
Unit
Note
-8
-H
-L
-10
Operating current
(One bank active)
I
CC1
Burst length = 1
t
RC
≥
t
RC
(min)
I
OL
= 0 mA
105
95
95
90
mA
1
Precharge standby current in
power-down mode
I
CC2
P
CKE
≤
V
IL
(max), t
CC
= 15ns
1
mA
I
CC2
PS
CKE & CLK
≤
V
IL
(max), t
CC
=
∞
1
Precharge standby current in
non power-down mode
I
CC2
N
CKE
≥
V
IH
(min), CS
≥
V
IH
(min), t
CC
= 15ns
Input signals are changed one time during 30ns
20
mA
I
CC2
NS
CKE
≥
V
IH
(min), CLK
≤
V
IL
(max), t
CC
=
∞
Input signals are stable
10
Active standby current in
power-down mode
I
CC3
P
CKE
≤
V
IL
(max), t
CC
= 15ns
2
mA
I
CC3
PS
CKE & CLK
≤
V
IL
(max), t
CC
=
∞
2
Active standby current in
non power-down mode
(One bank active)
I
CC3
N
CKE
≥
V
IH
(min), CS
≥
V
IH
(min), t
CC
= 15ns
Input signals are changed one time during 30ns
30
mA
I
CC3
NS
CKE
≥
V
IH
(min), CLK
≤
V
IL
(max), t
CC
=
∞
Input signals are stable
20
mA
Operating current
(Burst mode)
I
CC4
I
OL
= 0 mA
Page burst
2Banks activated
t
CCD
= 2CLKs
3
125
105
105
105
mA
1
2
95
105
95
90
Refresh current
I
CC5
t
RC
≥
t
RC
(min)
150
135
mA
2
Self refresh current
I
CC6
CKE
≤
0.2V
1
mA
3
450
uA
4
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