參數(shù)資料
型號: KM48S8020B
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 4M x 8Bit x 2 Banks Synchronous DRAM(4M x 8位 x 2組同步動態(tài)RAM)
中文描述: 4米× 8位× 2銀行同步DRAM(4米× 8位× 2組同步動態(tài)RAM)的
文件頁數(shù): 40/43頁
文件大?。?/td> 604K
代理商: KM48S8020B
ELECTRONICS
REV. 2 Mar. '98
TIMING DIAGRAM - II
CMOS SDRAM
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
Burst Read Single bit Write Cycle @Burst Length=2
HIGH
Row Active
(A-Bank)
Row Active
(A-Bank)
Write with
Auto Precharge
(B-Bank)
: Don't care
*Note :
1. BRSW modes is enabled by setting A
9
"High" at MRS (Mode Register Set).
At the BRSW Mode, the burst length at write is fixed to "1" regaredless of programmed burst length.
2. When BRSW write command with auto precharge is executed, keep it in mind that t
Auto precharge is executed at the burst-end cycle, so in the case of BRSW write command,
the next cycle starts the precharge.
RAS
should not be violated.
Write
(A-Bank)
*Note 1
Row Active
(B-Bank)
Read
(A-Bank)
Read with
Auto Precharge
(A-Bank)
Precharge
(A-Bank)
*Note 2
BA
A
10
/AP
CL=2
CL=3
DQ
ADDR
CAS
RAS
CS
CKE
CLOCK
WE
DQM
DAa0
DAa0
QAb0
QAb1
QAb0
QAb1
DBc0
DBc0
QAd0
QAd1
QAd0
QAd1
RAa
CAa
RBb
CAb
RAc
CBc
CAd
RAc
RAa
RBb
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