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參數(shù)資料
| 型號(hào)： | K9E2G08U0M-YIB00 |
| 元件分類： | PROM |
| 英文描述： | 256M X 8 FLASH 2.7V PROM, 30 ns, PDSO48 |
| 封裝： | 12 X 20 MM, 0.50 MM PITCH, PLASTIC, TSOP1-48 |
| 文件頁數(shù)： | 35/38頁 |
| 文件大?。?/td> | 888K |
| 代理商： | K9E2G08U0M-YIB00 |
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FLASH MEMORY
6
K9E2G08U0M
Preliminary
512Bytes
16 Bytes
Figure 1. K9E2G08U0M FUNCTIONAL BLOCK DIAGRAM
Figure 2. K9E2G08U0M ARRAY ORGANIZATION
VCC
X-Buffers
2G + 64M Bits
Command
NAND Flash
ARRAY
(512 + 16)Bytes x 524,288
Y-Gating
Page Register & S/A
I/O Buffers & Latches
Y-Buffers
Control Logic
Global Buffers
Output
Driver
VSS
A9 - A27
A0 - A7
Command
CE
RE
WE
WP
I/0 0
I/0 7
VCC/VCCQ
VSS
A8
1st half Page Register
(=256 Bytes)
2nd half Page Register
(=256 Bytes)
256K Pages
(=8,192 Blocks)
512 Bytes
8 bits
16 Bytes
1 Block = 32 Pages
= (16K + 512) Bytes
I/O 0 ~ I/O 7
1 Page = 528 Bytes
1 Block = 528 Bytes x 32 Pages
= (16K + 512) Bytes
1 Device = 528Bytes x 32Pages x 16,384 Blocks
= 2,112 Mbits
Column Address
Row Address
(Page Address)
Page Register
CLE ALE
NOTE : Column Address : Starting Address of the Register.
00h Command(Read) : Defines the starting address of the 1st half of the register.
01h Command(Read) : Defines the starting address of the 2nd half of the register.
* A8 is set to "Low" or "High" by the 00h or 01h Command.
* L must be set to "Low".
* The device ignores any additional input of address cycles than reguired.
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
1st Cycle
A0
A1
A2
A3
A4
A5
A6
A7
2nd Cycle
A9
A10
A11
A12
A13
A14
A15
A16
3rd Cycle
A17
A18
A19
A20
A21
A22
A23
A24
4th Cycle
A25
A26
A27
*L
Register
& High Voltage
Generator
Latches
& Decoders
Latches
& Decoders
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