- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄296260 > K9E2G08U0M-YIB00 256M X 8 FLASH 2.7V PROM, 30 ns, PDSO48 PDF資料下載
參數(shù)資料
| 型號： | K9E2G08U0M-YIB00 |
| 元件分類： | PROM |
| 英文描述： | 256M X 8 FLASH 2.7V PROM, 30 ns, PDSO48 |
| 封裝： | 12 X 20 MM, 0.50 MM PITCH, PLASTIC, TSOP1-48 |
| 文件頁數(shù)： | 2/38頁 |
| 文件大?。?/td> | 888K |
| 代理商： | K9E2G08U0M-YIB00 |
第1頁當前第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁
FLASH MEMORY
10
K9E2G08U0M
Preliminary
CAPACITANCE(TA=25°C, VCC=3.3V, f=1.0MHz)
NOTE : Capacitance is periodically sampled and not 100% tested.
Item
Symbol
Test Condition
Min
Max
Unit
Input/Output Capacitance
CI/O
VIL=0V
-
10
pF
Input Capacitance
CIN
VIN=0V
-
10
pF
VALID BLOCK
NOTE :
1. The K9E2G08U0M may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks
is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase or
program factory-marked bad blocks. Refer to the attached technical notes for a appropriate management of invalid blocks.
2. The 1st block, which is placed on 00h block address, is fully guaranteed to be a valid block, does not require Error Correction up to 1K Program/Erase
cycles.
3. Minimum 2,013 valid blocks are guaranteed for each contiguous 256Mb memory space.
Parameter
Symbol
Min
Typ.
Max
Unit
Valid Block Number
NVB
16,104
-
16,384
Blocks
AC TEST CONDITION
(K9E2G08U0M-XCB0 :TA=0 to 70
°C, K9E2G08U0M-XIB0:TA=-40 to 85°C)
Parameter
Value
Input Pulse Levels
0.4V to 2.4V
Input Rise and Fall Times
5ns
Input and Output Timing Levels
1.5V
Output Load
VccQ=3.0V+/-10% : 1 TTL GATE and CL= 50pF
VccQ=3.3V+/-10% : 1 TTL GATE and CL=100pF
MODE SELECTION
NOTE : 1. X can be VIL or VIH.
2. WP should be biased to CMOS high or CMOS low for standby.
CLE
ALE
CE
WE
RE
WP
Mode
HL
L
H
X
Read Mode
Command Input
L
H
L
H
X
Address Input (4 clocks)
HL
L
H
Write Mode
Command Input
L
H
L
H
Address Input (4 clocks)
L
H
Data Input
L
H
X
Data Output
L
H
X
During Read (Busy)
X
H
During Program (Busy)
X
H
During Erase (Busy)
X
X(1)
X
L
Write Protect
XX
HX
X
0V/VCC(2) Stand-by
Program / Erase Characteristics
Parameter
Symbol
Min
Typ
Max
Unit
Program Time
tPROG(1)
-
200
500
s
Dummy Busy Time for Multi Plane Program
tDBSY
110
s
Number of Partial Program Cycles
in the Same Page
Main Array
Nop
-
1
cycle
Spare Array
-
2
cycle
Block Erase Time
tBERS
-2
3
ms
NOTE : 1.Typical Program time is defined as the time within which more than 50% of the whole pages are programmed at Vcc of 3.3V and 25’c
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| KA-59-281 | TNC CONNECTOR, PLUG |
| KA-91-02 | RF STRAIGHT ADAPTER |
| KA-91-16 | RF TEE ADAPTER |
| KA-99-24 | RF STRAIGHT ADAPTER |
| KA10R25 | 250 A, SILICON SURGE PROTECTOR |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| K9F1208B0B | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:FLASH MEMORY |
| K9F1208B0C | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:64M x 8 Bits NAND Flash Memory |
| K9F1208B0C-P | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:FLASH MEMORY |
| K9F1208D0A | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:64M x 8 Bit , 32M x 16 Bit NAND Flash Memory |
| K9F1208D0A-P | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:64M x 8 Bit , 32M x 16 Bit NAND Flash Memory |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。