參數(shù)資料
型號(hào)： ISPPAC-CLK5610V-01T100I
廠商： Lattice Semiconductor Corporation
英文描述： Linear Array Light; LED Color:Blue; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No; Supply Current:1.6A; Supply Voltage:24VDC; Wavelength:470nm
中文描述： 在系統(tǒng)可編程，零延遲時(shí)鐘發(fā)生器通用扇出緩沖器
文件頁(yè)數(shù)： 17/47頁(yè)
文件大?。?/td> 871K
代理商： ISPPAC-CLK5610V-01T100I
Lattice Semiconductor
ispClock5600 Family Data Sheet
17
M, N, and V Dividers
The ispClock5600 incorporates a set of programmable dividers which provide the ability to synthesize output fre-
quencies differing from that of the reference clock input.
The input, or M divider prescales the input reference frequency, and can be programmed with integer values over
the range of 1 to 32. To achieve low levels of output jitter, it is best to use the smallest M divider value possible.
The feedback, or N divider prescales the feedback frequency and like the M divider, can also be programmed with
integer values ranging from 1 to 32.
Each one of the
fi
ve output, or V dividers can be independently programmed to provide even division ratios ranging
from 2 to 64.
When the PLL is selected (PLL_BYPASS=LOW) and locked, the output frequency of each V divider (f
k
) may be cal-
culated as:
(1)
where
f
k
is the frequency of V divider k
f
ref
is the input reference frequency
M and N are the input and feedback divider settings
V
fbk
is the setting of the V divider used to close the PLL feedback path
V
k
is the setting of the V divider used to provide output k
Note that because the feedback may be taken from any V divider, V
k
and V
fbk
may refer to the same divider.
Because the VCO has an operating frequency range spanning 320 MHz to 640 MHz, and the V dividers provide
division ratios from 2 to 64, the ispClock5600 can generate output signals ranging from 5MHz to 320 MHz. For per-
formance and stability reasons, however, there are several constraints which should be followed when selecting
divider values:
Use the smallest feasible value for the M divider
The output frequency from the M (and N) divider should be greater or equal to 10 MHz.
The product of the N divider and the V divider used to close the PLLs feedback loop should be less than or
equal to 64 (N x V
fbk
≤
64)
Output Duty Cycle
The ispClock5600’s output duty cycle varies as a function of the V divider used to generate that output. If the V-
divider setting is either 2 or a multiple of 4, the nominal output duty cycle will be exactly 50%. All other V divider set-
tings will result in non-50% output duty cycles. Table 3 summarizes the nominal output duty cycle as a function of
the V divider setting. Note that if the output is inverted, the duty cycle will be equal to 100%-DC%, where DC% is
the duty cycle indicated in the table. For example, with a V divider of 14, the non-inverted duty cycle from Table 3
will be 43%. For an inverted output, the duty cycle will be 100%-43% or 57%.
=
f
k
f
ref
N x V
fbk
M x V
k
相關(guān)PDF資料
PDF描述
ISPCLOCK5600 In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer
ISPPAC-CLK5610V-01T100C In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer
ISPPAC-CLK5620V-01T100C LED Area Light; LED Color:Blue; Leaded Process Compatible:No; Light Emitting Area:80x80mm; Peak Reflow Compatible (260 C):No; Supply Current:250mA; Supply Voltage:24VDC; Wavelength:470nm
ISPPAC-CLK5620V-01T100I In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer
ISPPAC-CLK5610V-01T48C Spot Light; LED Color:Blue; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No; Supply Current:160mA; Supply Voltage:30VDC; Wavelength:470nm
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ISPPAC-CLK5610V-01T48C 功能描述:時(shí)鐘驅(qū)動(dòng)器及分配 3.3V 10-320MHz RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel
ISPPAC-CLK5610V-01T48I 功能描述:時(shí)鐘驅(qū)動(dòng)器及分配 PROGRAMMABLE ZERO DELAY CL GEN RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel
ISPPAC-CLK5610V-01TN100C 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer
ISPPAC-CLK5610V-01TN100I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer
ISPPAC-CLK5610V-01TN48C 功能描述:時(shí)鐘驅(qū)動(dòng)器及分配 PROGRAMMABLE ZERO DELAY CL GEN RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel
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