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參數(shù)資料
| 型號： | ISPPAC-CLK5610V-01T100I |
| 廠商： | Lattice Semiconductor Corporation |
| 英文描述： | Linear Array Light; LED Color:Blue; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No; Supply Current:1.6A; Supply Voltage:24VDC; Wavelength:470nm |
| 中文描述： | 在系統(tǒng)可編程，零延遲時鐘發(fā)生器通用扇出緩沖器 |
| 文件頁數(shù)： | 14/47頁 |
| 文件大?。?/td> | 871K |
| 代理商： | ISPPAC-CLK5610V-01T100I |
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Lattice Semiconductor
ispClock5600 Family Data Sheet
14
Typical Performance Characteristics
Detailed Description
PLL Subsystem
The ispClock5600 provides an integral phase-locked-loop (PLL) which may be used to generate output clock sig-
nals at lower, higher, or the same frequency as a user-supplied input reference signal. The core functions of the
PLL are an edge-sensitive phase detector, a programmable loop
fi
lter, and a high-speed voltage-controlled oscilla-
tor (VCO). Additionally, a set of programmable input, output and feedback dividers (M, N, V[1..5]) is provided to
support the synthesis of different output frequencies.
Phase/Frequency Detector
The ispClock5600 provides an edge-sensitive phase/frequency detector (PFD), which means that the device will
function properly over a wide range of input clock reference duty cycles. It is only necessary that the input refer-
ence clock meet speci
fi
ed minimum HIGH and LOW times (t
CLOCKHI,
t
CLOCKLO
) for it to be properly recognized by
the PFD. The PFD’s output is of a classical charge-pump type, outputting charge packets which are then integrated
by the PLL‘s loop
fi
lter.
A lock-detection feature is also associated with the PFD. When the ispClock5600 is in a LOCKED state, the LOCK
output pin goes LOW. The lock detector has two operating modes; phase lock mode and frequency lock mode. In
phase-lock mode, the LOCK signal is asserted if the phases of the reference and feedback signals match, whereas
in frequency-lock mode the LOCK signal is asserted when the frequencies of the feedback and reference signals
0
0.2
0.4
0.6
0.8
1
1.2
300
0
3
6
9
12
15
400
500
600
700
I
CCO
vs. Output Frequency
(LVCMOS 3.3V, Normalized to 320MHz)
I
CCD
vs. f
VCO
(Normalized to 640MHz)
Typical Skew Error vs. Setting
(Skew Mode = FINE, f
VCO
= 600MHz)
0
0.2
0.4
0.6
0.8
1
1.2
0
50
100
150
200
250
300
350
Output Frequency (MHz)
Skew Setting #
f
VCO
(MHz)
N
N
E
-100
-75
-50
-25
0
25
50
75
100
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ISPCLOCK5600 | In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer |
| ISPPAC-CLK5610V-01T100C | In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer |
| ISPPAC-CLK5620V-01T100C | LED Area Light; LED Color:Blue; Leaded Process Compatible:No; Light Emitting Area:80x80mm; Peak Reflow Compatible (260 C):No; Supply Current:250mA; Supply Voltage:24VDC; Wavelength:470nm |
| ISPPAC-CLK5620V-01T100I | In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer |
| ISPPAC-CLK5610V-01T48C | Spot Light; LED Color:Blue; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No; Supply Current:160mA; Supply Voltage:30VDC; Wavelength:470nm |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISPPAC-CLK5610V-01T48C | 功能描述:時鐘驅(qū)動器及分配 3.3V 10-320MHz RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| ISPPAC-CLK5610V-01T48I | 功能描述:時鐘驅(qū)動器及分配 PROGRAMMABLE ZERO DELAY CL GEN RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| ISPPAC-CLK5610V-01TN100C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer |
| ISPPAC-CLK5610V-01TN100I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer |
| ISPPAC-CLK5610V-01TN48C | 功能描述:時鐘驅(qū)動器及分配 PROGRAMMABLE ZERO DELAY CL GEN RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
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