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參數(shù)資料
| 型號： | ISPPAC-CLK5520V-01TN100I |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | 時鐘及定時 |
| 英文描述： | LED Area Light; LED Color:Infrared; Leaded Process Compatible:No; Light Emitting Area:62x62mm; Peak Reflow Compatible (260 C):No; Supply Current:150mA; Supply Voltage:24VDC; Wavelength:940nm |
| 中文描述： | 5500 SERIES, PLL BASED CLOCK DRIVER, 20 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP100 |
| 封裝： | LEAD FREE, TQFP-100 |
| 文件頁數(shù)： | 31/43頁 |
| 文件大?。?/td> | 867K |
| 代理商： | ISPPAC-CLK5520V-01TN100I |
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Lattice Semiconductor
ispClock5500 Family Data Sheet
31
IEEE Standard 1149.1 Interface (JTAG)
Serial Port Programming Interface Communication with the ispClock5500 is facilitated via an IEEE 1149.1 test
access port (TAP). It is used by the ispClock5500 both as a serial programming interface, and for boundary scan
test purposes. A brief description of the ispClock5500 JTAG interface follows. For complete details of the reference
speci
fi
cation, refer to the publication, Standard Test Access Port and Boundary-Scan Architecture, IEEE Std.
1149.1-1990 (which now includes IEEE Std. 1149.1a-1993).
Overview
An IEEE 1149.1 test access port (TAP) provides the control interface for serially accessing the digital I/O of the
ispClock5500. The TAP controller is a state machine driven with mode and clock inputs. Given in the correct
sequence, instructions are shifted into an instruction register which then determines subsequent data input, data
output, and related operations. Device programming is performed by addressing the con
fi
guration register, shifting
data in, and then executing a program con
fi
guration instruction, after which the data is transferred to internal
E
2
CMOS cells. It is these non-volatile cells that store the con
fi
guration or the ispClock5500. A set of instructions
are de
fi
ned that access all data registers and perform other internal control operations. For compatibility between
compliant devices, two data registers are mandated by the IEEE 1149.1 speci
fi
cation. Others are functionally spec-
i
fi
ed, but inclusion is strictly optional. Finally, there are provisions for optional data registers de
fi
ned by the manu-
facturer. The two required registers are the bypass and boundary-scan registers. Figure 28 shows how the
instruction and various data registers are organized in an ispClock5500.
Figure 28. ispClock5500 TAP Registers
TAP Controller Speci
fi
cs
The TAP is controlled by the Test Clock (TCK) and Test Mode Select (TMS) inputs. These inputs determine whether
an Instruction Register or Data Register operation is performed. Driven by the TCK input, the TAP consists of a
small 16-state controller design. In a given state, the controller responds according to the level on the TMS input as
shown in Figure 29. Test Data In (TDI) and TMS are latched on the rising edge of TCK, with Test Data Out (TDO)
becoming valid on the falling edge of TCK. There are six steady states within the controller: Test-Logic-Reset, Run-
ADDRESS REGISTER (10 BITS)
E
2
CMOS
NON-VOLATILE
MEMORY
UES REGISTER (32 BITS)
IDCODE REGISTER (32 BITS)
BYPASS REGISTER (1 BIT)
INSTRUCTION REGISTER (8 BITS)
TEST ACCESS PORT (TAP)
LOGIC
OUTPUT
LATCH
TDI
TCK
TMS
TDO
B-SCAN REGISTER (56 BITS)
M
DATA REGISTER (90 BITS)
相關(guān)PDF資料 |
PDF描述 |
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| ISPPAC-CLK5510V-01TN48C | Backlight LED; Color:Infrared; Digit/Alpha Height:85mm; Forward Current:500mA; Operating Temperature Range:0 C to +50 C; Leaded Process Compatible:No; Light Emitting Area:85x220mm; Peak Reflow Compatible (260 C):No |
| ISPPAC-CLK5510V-01TN48I | LED Area Light; Forward Current:300mA; Operating Temperature Range:0 C to +50 C; LED Color:Red; Leaded Process Compatible:No; Light Emitting Area:80x80mm; Peak Reflow Compatible (260 C):No; Supply Current:250mA |
| ISPPAC-CLK5610V-01T100I | Linear Array Light; LED Color:Blue; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No; Supply Current:1.6A; Supply Voltage:24VDC; Wavelength:470nm |
| ISPCLOCK5600 | In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer |
| ISPPAC-CLK5610V-01T100C | In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISPPACCLK5520V-01TN100I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Clock Generator with Universal Fan-Out Buffer |
| ISPPACCLK5520V-01TN48C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Clock Generator with Universal Fan-Out Buffer |
| ISPPACCLK5520V-01TN48I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Clock Generator with Universal Fan-Out Buffer |
| ISPPAC-CLK55XX | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Clock Generator with Universal Fan-Out Buffer |
| ISPPACCLK5610AV-01T100C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Enhanced Zero-Delay, Clock Generator with Universal Fan-Out Buffer |
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