參數(shù)資料
型號(hào)： ISPPAC-CLK5520V-01TN100I
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： 時(shí)鐘及定時(shí)
英文描述： LED Area Light; LED Color:Infrared; Leaded Process Compatible:No; Light Emitting Area:62x62mm; Peak Reflow Compatible (260 C):No; Supply Current:150mA; Supply Voltage:24VDC; Wavelength:940nm
中文描述： 5500 SERIES, PLL BASED CLOCK DRIVER, 20 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP100
封裝： LEAD FREE, TQFP-100
文件頁(yè)數(shù)： 15/43頁(yè)
文件大小： 867K
代理商： ISPPAC-CLK5520V-01TN100I
Lattice Semiconductor
ispClock5500 Family Data Sheet
15
match. The option of which mode to use is programmable and may be set using PAC-Designer software (available
from Lattice’s web site at www.latticesemi.com).
In phase-lock mode the lock detector asserts the LOCK signal as soon as a lock condition is determined. In fre-
quency-lock mode, however, the PLL must be in a locked condition for a set number of phase detector cycles
before the LOCK signal will be asserted. The number of cycles required before asserting the LOCK signal in fre-
quency-lock mode can be set from 16 through 256, in increments of 16.
When the lock condition is lost the LOCK signal will be de-asserted immediately both in phase and frequency-lock
modes.
Loop Filter
A simpli
fi
ed schematic for the ispClock5500 loop
fi
lter is shown in Figure 11. The
fi
lter’s capacitors are
fi
xed, and
the response is controlled by setting the value of the phase-detector’s output current source’s and the value of the
variable resistor. The phase detector output current has 14 possible settings, ranging from 3μA to 55μA, while the
resistor may be set to any one of six values ranging from 2.3K to 9.3K. This provides a total of 84 unique I-R com-
binations which may be selected.
Figure 11. ispClock5500 Loop Filter (Simplified)
Because the selection of an optimal PLL loop
fi
lter can be a daunting task, PAC-Designer software offers a set of
default
fi
lter settings which will provide acceptable performance for most applications. The primary criterion for
selecting one of these settings is the total division factor used in the feedback path, or the ratio between the VCO
output frequency and the frequency output by the N feedback divider (N x V
feedback
). Table 2 lists these default set-
tings and conditions under which they should be used.
Table 2. PAC-Designer Recommended Loop Filter Settings
N x V
FBK
2 to 8
I (μA)
R (k
)
2.3
5
10
7
2.3
12 to 14
9
2.3
16
11
2.3
18 to 20
13
2.3
22
15
2.3
24 to 26
17
2.3
28
19
2.3
30
21
2.3
32 to 64
22
2.3
To VCO
R
C
2
C
1
I
I
Phase Detector
From
M-divider
From
N-divider
相關(guān)PDF資料
PDF描述
ISPPAC-CLK5510V-01TN48C Backlight LED; Color:Infrared; Digit/Alpha Height:85mm; Forward Current:500mA; Operating Temperature Range:0 C to +50 C; Leaded Process Compatible:No; Light Emitting Area:85x220mm; Peak Reflow Compatible (260 C):No
ISPPAC-CLK5510V-01TN48I LED Area Light; Forward Current:300mA; Operating Temperature Range:0 C to +50 C; LED Color:Red; Leaded Process Compatible:No; Light Emitting Area:80x80mm; Peak Reflow Compatible (260 C):No; Supply Current:250mA
ISPPAC-CLK5610V-01T100I Linear Array Light; LED Color:Blue; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No; Supply Current:1.6A; Supply Voltage:24VDC; Wavelength:470nm
ISPCLOCK5600 In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer
ISPPAC-CLK5610V-01T100C In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ISPPACCLK5520V-01TN100I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Clock Generator with Universal Fan-Out Buffer
ISPPACCLK5520V-01TN48C 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Clock Generator with Universal Fan-Out Buffer
ISPPACCLK5520V-01TN48I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Clock Generator with Universal Fan-Out Buffer
ISPPAC-CLK55XX 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Clock Generator with Universal Fan-Out Buffer
ISPPACCLK5610AV-01T100C 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Enhanced Zero-Delay, Clock Generator with Universal Fan-Out Buffer
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