參數資料
型號： ISPPAC-CLK5520V-01TN100I
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： 時鐘及定時
英文描述： LED Area Light; LED Color:Infrared; Leaded Process Compatible:No; Light Emitting Area:62x62mm; Peak Reflow Compatible (260 C):No; Supply Current:150mA; Supply Voltage:24VDC; Wavelength:940nm
中文描述： 5500 SERIES, PLL BASED CLOCK DRIVER, 20 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP100
封裝： LEAD FREE, TQFP-100
文件頁數： 11/43頁
文件大?。?/td> 867K
代理商： ISPPAC-CLK5520V-01TN100I
Lattice Semiconductor
ispClock5500 Family Data Sheet
11
Timing Speci
fi
cations
Skew Matching
Programmable Skew Control
Control Functions
Figure 6. RESET and Profile Select Timing
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
t
SKEW
Output-output Skew
Between any two identically con
fi
gured and loaded
outputs regardless of bank and output frequency
—
—
50
ps
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
t
SKRANGE
Skew Control Range
1
Fine Skew Mode, f
VCO
= 320 MHz
Fine Skew Mode, f
VCO
= 640 MHz
Coarse Skew Mode, f
VCO
= 320 MHz
Coarse Skew Mode, f
VCO
= 640 MHz
—
5.86
—
ns
—
2.93
—
—
11.72
—
—
5.86
—
SK
STEPS
Skew Steps per range
—
16
—
t
SKSTEP
Skew Step Size
2
Fine Skew Mode, f
VCO
= 320 MHz
Fine Skew Mode, f
VCO
= 640 MHz
Coarse Skew Mode, f
VCO
= 320 MHz
Coarse Skew Mode, f
VCO
= 640 MHz
Fine skew mode
—
390
—
ps
—
195
—
—
780
—
—
390
—
t
SKERR
Skew Time Accuracy
3
—
30
—
ps
Coarse skew mode
—
50
—
1. Skew control range is a function of VCO frequency (f
VCO
). In
fi
ne skew mode T
SKRANGE
= 15/(8 x f
VCO
).
In coarse skew mode T
SKRANGE
= 15/(4 x f
VCO
).
2. Skew step size is a function of VCO frequency (f
VCO
). In
fi
ne skew mode T
SKSTEP
= 1/(8 x f
VCO
).
In coarse skew mode T
SKSTEP
= 1/(4 x f
VCO
).
3. Only applicable to outputs with non-zero skew settings.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
t
DIS/OE
Delay Time, OEX or OEY to Output Disabled/
Enabled
—
10
20
ns
t
DIS/GOE
Delay Time, GOE to Output Disabled/Enabled
—
10
20
ns
t
SUSGATE
Setup Time, SGATE to Output Clock Start/
Stop
3
—
—
cycles
1
t
PLL_RSTW
t
HPS_RST
1. Output clock cycles for the particular output being controlled.
PLL Reset Pulse Width
15
—
—
μs
Hold time for RESET past change in PS[0..1]
20
—
—
ns
t
HPS_RST
t
PLL_RSTW
PS[0..1]
RESET
相關PDF資料
PDF描述
ISPPAC-CLK5510V-01TN48C Backlight LED; Color:Infrared; Digit/Alpha Height:85mm; Forward Current:500mA; Operating Temperature Range:0 C to +50 C; Leaded Process Compatible:No; Light Emitting Area:85x220mm; Peak Reflow Compatible (260 C):No
ISPPAC-CLK5510V-01TN48I LED Area Light; Forward Current:300mA; Operating Temperature Range:0 C to +50 C; LED Color:Red; Leaded Process Compatible:No; Light Emitting Area:80x80mm; Peak Reflow Compatible (260 C):No; Supply Current:250mA
ISPPAC-CLK5610V-01T100I Linear Array Light; LED Color:Blue; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No; Supply Current:1.6A; Supply Voltage:24VDC; Wavelength:470nm
ISPCLOCK5600 In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer
ISPPAC-CLK5610V-01T100C In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer
相關代理商/技術參數
參數描述
ISPPACCLK5520V-01TN100I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Clock Generator with Universal Fan-Out Buffer
ISPPACCLK5520V-01TN48C 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Clock Generator with Universal Fan-Out Buffer
ISPPACCLK5520V-01TN48I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Clock Generator with Universal Fan-Out Buffer
ISPPAC-CLK55XX 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Clock Generator with Universal Fan-Out Buffer
ISPPACCLK5610AV-01T100C 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Enhanced Zero-Delay, Clock Generator with Universal Fan-Out Buffer
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