參數(shù)資料
型號(hào)： ISPPAC-CLK5520V-01TN100I
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： 時(shí)鐘及定時(shí)
英文描述： LED Area Light; LED Color:Infrared; Leaded Process Compatible:No; Light Emitting Area:62x62mm; Peak Reflow Compatible (260 C):No; Supply Current:150mA; Supply Voltage:24VDC; Wavelength:940nm
中文描述： 5500 SERIES, PLL BASED CLOCK DRIVER, 20 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP100
封裝： LEAD FREE, TQFP-100
文件頁(yè)數(shù)： 12/43頁(yè)
文件大小： 867K
代理商： ISPPAC-CLK5520V-01TN100I
Lattice Semiconductor
ispClock5500 Family Data Sheet
12
Timing Speci
fi
cations (Cont.)
Boundary Scan Logic
JTAG Interface and Programming Mode
Symbol
Parameter
Min.
Max.
Units
t
BTCP
t
BTCH
t
BTCL
t
BTSU
t
BTH
t
BRF
t
BTCO
t
BTOZ
t
BTVO
t
BVTCPSU
t
BTCPH
t
BTUCO
t
BTUOZ
t
BTUOV
TCK (BSCAN Test) Clock Cycle
40
—
ns
TCK (BSCAN Test) Pulse Width High
20
—
ns
TCK (BSCAN Test) Pulse Width Low
20
—
ns
TCK (BSCAN Test) Setup Time
8
—
ns
TCK (BSCAN Test) Hold Time
10
—
ns
TCK (BSCAN Test) Rise and Fall Rate
50
—
mV/ns
TAP Controller Falling Edge of Clock to Valid Output
—
10
ns
TAP Controller Falling Edge of Clock to Data Output Disable
—
10
ns
TAP Controller Falling Edge of Clock to Data Output Enable
—
10
ns
BSCAN Test Capture Register Setup Time
8
—
ns
BSCAN Test Capture Register Hold Time
10
—
ns
BSCAN Test Update Register, Falling Edge of Clock to Valid Output
—
25
ns
BSCAN Test Update Register, Falling Edge of Clock to Output Disable
—
25
ns
BSCAN Test Update Register, Falling Edge of Clock to Output Enable
—
25
ns
Symbol
Parameter
Condition
Min.
Typ.
Max.
Units
f
MAX
t
CKH
t
CKL
t
ISPEN
t
ISPDIS
t
HVDIS
t
HVDIS
t
CEN
t
CDIS
t
SU1
t
H
t
CO
t
PWV
t
PWP
t
BEW
Maximum TCK Clock Frequency
—
—
25
MHz
TCK Clock Pulse Width, High
20
—
—
ns
TCK Clock Pulse Width, Low
20
—
—
ns
Program Enable Delay Time
15
—
—
μs
Program Disable Delay Time
30
—
—
μs
High Voltage Discharge Time, Program
30
—
—
μs
High Voltage Discharge Time, Erase
200
—
—
μs
Falling Edge of TCK to TDO Active
—
—
15
ns
Falling Edge of TCK to TDO Disable
—
—
15
ns
Setup Time
8
—
—
ns
Hold Time
10
—
—
ns
Falling Edge of TCK to Valid Output
—
—
15
ns
Verify Pulse Width
30
—
—
μs
Programming Pulse Width
10
—
—
ms
Bulk Erase Pulse Width
200
—
—
ms
相關(guān)PDF資料
PDF描述
ISPPAC-CLK5510V-01TN48C Backlight LED; Color:Infrared; Digit/Alpha Height:85mm; Forward Current:500mA; Operating Temperature Range:0 C to +50 C; Leaded Process Compatible:No; Light Emitting Area:85x220mm; Peak Reflow Compatible (260 C):No
ISPPAC-CLK5510V-01TN48I LED Area Light; Forward Current:300mA; Operating Temperature Range:0 C to +50 C; LED Color:Red; Leaded Process Compatible:No; Light Emitting Area:80x80mm; Peak Reflow Compatible (260 C):No; Supply Current:250mA
ISPPAC-CLK5610V-01T100I Linear Array Light; LED Color:Blue; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No; Supply Current:1.6A; Supply Voltage:24VDC; Wavelength:470nm
ISPCLOCK5600 In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer
ISPPAC-CLK5610V-01T100C In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ISPPACCLK5520V-01TN100I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Clock Generator with Universal Fan-Out Buffer
ISPPACCLK5520V-01TN48C 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Clock Generator with Universal Fan-Out Buffer
ISPPACCLK5520V-01TN48I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Clock Generator with Universal Fan-Out Buffer
ISPPAC-CLK55XX 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Clock Generator with Universal Fan-Out Buffer
ISPPACCLK5610AV-01T100C 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable, Enhanced Zero-Delay, Clock Generator with Universal Fan-Out Buffer
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