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參數(shù)資料
| 型號： | ISPPAC-CLK5510V-01TN48I |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | 時鐘及定時 |
| 英文描述： | LED Area Light; Forward Current:300mA; Operating Temperature Range:0 C to +50 C; LED Color:Red; Leaded Process Compatible:No; Light Emitting Area:80x80mm; Peak Reflow Compatible (260 C):No; Supply Current:250mA |
| 中文描述： | 5500 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP48 |
| 封裝： | LEAD FREE, TQFP-48 |
| 文件頁數(shù)： | 37/43頁 |
| 文件大?。?/td> | 867K |
| 代理商： | ISPPAC-CLK5510V-01TN48I |
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Lattice Semiconductor
ispClock5500 Family Data Sheet
37
Detailed Pin Descriptions
VCCO_[0..9], GNDO_[0..9]
– These pins provide power and ground for each of the output banks. In the case when
an output bank is unused, its corresponding VCCO pin may be left unconnected or preferably should be tied to
ground. ALL GNDO pins should be tied to ground regardless of whether the associated bank is used or not. When
a bank is used, it should be individually bypassed with a capacitor in the range of 0.01 to 0.1uF as close to its
VCCO and GNDO pins as is practical.
BANK_[0..9]A, BANK_[0..9]B
– These pins provide clock output signals. The choice of output divider (V0-V4) and
output driver type (CMOS, LVDS, SSTL, etc.) may be selected on a bank-by-bank basis. When the outputs are con-
fi
gured as pairs of single-ended outputs, output impedance and slew rate may be selected on an output-by-output
basis.
VCCD
Digital Core VCC
Power
24, 33
47, 71
GNDD
Digital GND
GND
15, 16, 17, 23, 48
32, 33, 34, 35, 36, 37,
46, 93
VCCJ
JTAG interface VCC
Power
36
74
REFA+
Clock Reference A positive input
Input
18
38
REFA-
Clock Reference A negative input
Input
19
39
REFB+
Clock Reference B positive input
Input
—
42
REFB-
Clock Reference B negative input
Input
Input
1
—
41
REFSEL
Clock Reference Select input (LVCMOS)
—
43
REFVTT
Termination voltage for reference inputs
Power
20
40
TDO
JTAG TDO Output line
Output
Input
2
35
73
TDI
JTAG TDI Input line
39
84
TCK
JTAG Clock Input
Input
Input
2
38
83
TMS
JTAG Mode Select
37
82
LOCK
PLL Lock indicator, LOW indicates PLL lock
Output
Input
1
Input
1
34
72
SGATE
Synchronous output gate
40
85
GOE
Global Output Enable
42
87
OEX
Output Enable 1
Input
21
44
OEY
Output Enable 2
Input
Input
1
Input
1
Input
1
22
45
PS0
Pro
fi
le Select 0
44
89
PS1
Pro
fi
le Select 1
43
88
PLL_BYPASS PLL Bypass
47
92
RESET
Reset PLL
Input
41
86
TEST1
Test Input 1 - connect to GNDD
Input
46
91
TEST2
Test Input 2 - connect to GNDD
Input
45
90
n/c
No internal connection
n/a
—
1, 2, 23, 24, 25, 26, 27,
28, 29, 48, 49, 50, 75,
76, 77, 78, 79, 94, 97,
98, 99, 100
Reserved
Factory use only - Do not connect
n/a
—
80, 81, 95, 96
1. Internal pull-down resistor.
2. Internal pull-up resistor.
Pin Descriptions (Continued)
Pin Name
Description
Pin Type
Pin Number
ispClock5510
48 TQFP
ispClock5520
100 TQFP
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ISPPAC-CLK5610V-01T100I | Linear Array Light; LED Color:Blue; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No; Supply Current:1.6A; Supply Voltage:24VDC; Wavelength:470nm |
| ISPCLOCK5600 | In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer |
| ISPPAC-CLK5610V-01T100C | In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer |
| ISPPAC-CLK5620V-01T100C | LED Area Light; LED Color:Blue; Leaded Process Compatible:No; Light Emitting Area:80x80mm; Peak Reflow Compatible (260 C):No; Supply Current:250mA; Supply Voltage:24VDC; Wavelength:470nm |
| ISPPAC-CLK5620V-01T100I | In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISPPACCLK5510V-01TN48I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Clock Generator with Universal Fan-Out Buffer |
| ISPPAC-CLK5520V-01T100C | 功能描述:時鐘驅(qū)動器及分配 PROGRAMMABLE CLOCK GENERATOR RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| ISPPACCLK5520V-01T100C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Clock Generator with Universal Fan-Out Buffer |
| ISPPAC-CLK5520V-01T100I | 功能描述:時鐘驅(qū)動器及分配 PROGRAMMABLE CLOCK GENERATOR RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| ISPPACCLK5520V-01T100I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Clock Generator with Universal Fan-Out Buffer |
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