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參數(shù)資料
| 型號(hào)： | ISPPAC-CLK5510V-01TN48I |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | LED Area Light; Forward Current:300mA; Operating Temperature Range:0 C to +50 C; LED Color:Red; Leaded Process Compatible:No; Light Emitting Area:80x80mm; Peak Reflow Compatible (260 C):No; Supply Current:250mA |
| 中文描述： | 5500 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP48 |
| 封裝： | LEAD FREE, TQFP-48 |
| 文件頁數(shù)： | 21/43頁 |
| 文件大?。?/td> | 867K |
| 代理商： | ISPPAC-CLK5510V-01TN48I |
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Lattice Semiconductor
ispClock5500 Family Data Sheet
21
Please note that while the above discussions specify using 50
termination impedances, the actual impedance
required to properly terminate the transmission line and maintain good signal integrity may vary from this ideal. The
actual impedance required will be a function of the driver used to generate the signal and the transmission medium
used (PCB traces, connectors and cabling). The ispClock5500’s ability to adjust input impedance over a range of
40
to 70
allows the user to adapt his circuit to non-ideal behaviors from the rest of the system without having to
swap out components.
Output Drivers
The ispClock5500 provide banks of con
fi
gurable, internally-terminated high-speed dual-output line drivers. The
ispClock5510 provides
fi
ve driver banks, while the ispClock5520 provides ten. Each of these driver banks may be
con
fi
gured to provide either a single differential output signal, or a pair of single-ended output signals. Programma-
ble internal source-series termination allows the ispClock5500 to be matched to transmission lines with imped-
ances ranging from 40 to 70 Ohms. The outputs may be independently enabled or disabled, either from E
2
CMOS
con
fi
guration or by external control lines. Additionally, each can be independently programmed to provide a
fi
xed
amount of signal delay or skew, allowing the user to compensate for the effects of unequal PCB trace lengths or
loading effects. Figure 18 shows a block diagram of a typical ispClock5500 output driver bank and associated skew
control.
Because of the high edge rates which can be generated by the ispClock5500’s clock output drivers, the VCCO
power supply pin for each output bank should be individually bypassed. Low ESR capacitors with values ranging
from 0.01 to 0.1 μF may be used for this purpose. Each bypass capacitor should be placed as close to its respec-
tive output bank power pins (VCCO and GNDO) pins as is possible to minimize interconnect length and associated
parasitic inductances.
In the case where an output bank is unused, the associated VCCO pin may be either left
fl
oating or tied to ground
to reduce quiescent power consumption. We recommend, however, that all unused VCCO pins be tied to ground
where possible. All GNDD pins must be tied to ground, regardless of whether or not the associated bank is used.
Figure 18. ispClock5500 Output Driver and Skew Control
OE
Control
From V-Dividers
Skew
Adjust
Skew
Adjust
BANKxA
BANKxB
Single-ended
‘A’ output Driver
Single-ended
‘B’ output Driver
Differential
(PECL/LVDS)
Driver
OE
Control
OE
Control
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ISPPAC-CLK5610V-01T100I | Linear Array Light; LED Color:Blue; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No; Supply Current:1.6A; Supply Voltage:24VDC; Wavelength:470nm |
| ISPCLOCK5600 | In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer |
| ISPPAC-CLK5610V-01T100C | In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer |
| ISPPAC-CLK5620V-01T100C | LED Area Light; LED Color:Blue; Leaded Process Compatible:No; Light Emitting Area:80x80mm; Peak Reflow Compatible (260 C):No; Supply Current:250mA; Supply Voltage:24VDC; Wavelength:470nm |
| ISPPAC-CLK5620V-01T100I | In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISPPACCLK5510V-01TN48I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Clock Generator with Universal Fan-Out Buffer |
| ISPPAC-CLK5520V-01T100C | 功能描述:時(shí)鐘驅(qū)動(dòng)器及分配 PROGRAMMABLE CLOCK GENERATOR RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| ISPPACCLK5520V-01T100C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Clock Generator with Universal Fan-Out Buffer |
| ISPPAC-CLK5520V-01T100I | 功能描述:時(shí)鐘驅(qū)動(dòng)器及分配 PROGRAMMABLE CLOCK GENERATOR RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| ISPPACCLK5520V-01T100I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Clock Generator with Universal Fan-Out Buffer |
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