參數(shù)資料
型號： ISPPAC-CLK5510V-01TN48I
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： 時鐘及定時
英文描述： LED Area Light; Forward Current:300mA; Operating Temperature Range:0 C to +50 C; LED Color:Red; Leaded Process Compatible:No; Light Emitting Area:80x80mm; Peak Reflow Compatible (260 C):No; Supply Current:250mA
中文描述： 5500 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP48
封裝： LEAD FREE, TQFP-48
文件頁數(shù)： 18/43頁
文件大?。?/td> 867K
代理商： ISPPAC-CLK5510V-01TN48I
Lattice Semiconductor
ispClock5500 Family Data Sheet
18
Figure 12. ispClock5500 Clock Reference Input Structure (REFA+/- Pair Shown)
The following usage guidelines are suggested for interfacing to supported logic families.
LVTTL (3.3V), LVCMOS (1.8V, 2.5V, 3.3V)
The receiver should be set to LVCMOS or LVTTL mode, and the input signal should be connected to the ‘+’ termi-
nal of the input pair (e.g. REFA+). The ‘-’ input terminal should be left
fl
oating. CMOS transmission lines are gener-
ally source terminated, so all termination resistors should be set to the OPEN state. Figure 13 shows the proper
con
fi
guration. Please note that because switching thresholds are different for LVCMOS running at 1.8V, there is a
separate con
fi
guration setting for this particular standard.
Figure 13. LVCMOS/LVTTL Input Receiver Configuration
HSTL, SSTL2, SSTL3
The receiver should be set to HSTL/SSTL mode, and the input signal should be fed into the ‘+’ terminal of the input
pair. The ‘-’ input terminal should be tied to the appropriate V
ref
value, and the REFVTT terminal should be tied to a
V
TT
termination supply. The positive input’s terminating resistor should be engaged and set to 50
. Figure 14
shows an appropriate con
fi
guration. Refer to the “Recommended Operating Conditions - Supported Logic Stan-
dards” table in this data sheet for suitable values of V
REF
and V
TT.
R
T
R
T
REFA-
REFA+
REFVTT
To Internal
Logic
Single-ended
Receiver
ispClock5500
Differential
Receiver
R
T
OPEN
REFA-
REFA+
REFVTT
Single-ended
Receiver
No Connect
No Connect
Signal In
ispClock5500
相關(guān)PDF資料
PDF描述
ISPPAC-CLK5610V-01T100I Linear Array Light; LED Color:Blue; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No; Supply Current:1.6A; Supply Voltage:24VDC; Wavelength:470nm
ISPCLOCK5600 In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer
ISPPAC-CLK5610V-01T100C In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer
ISPPAC-CLK5620V-01T100C LED Area Light; LED Color:Blue; Leaded Process Compatible:No; Light Emitting Area:80x80mm; Peak Reflow Compatible (260 C):No; Supply Current:250mA; Supply Voltage:24VDC; Wavelength:470nm
ISPPAC-CLK5620V-01T100I In-System Programmable, Zero-Delay Clock Generator with Universal Fan-Out Buffer
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ISPPACCLK5510V-01TN48I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Clock Generator with Universal Fan-Out Buffer
ISPPAC-CLK5520V-01T100C 功能描述:時鐘驅(qū)動器及分配 PROGRAMMABLE CLOCK GENERATOR RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel
ISPPACCLK5520V-01T100C 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Clock Generator with Universal Fan-Out Buffer
ISPPAC-CLK5520V-01T100I 功能描述:時鐘驅(qū)動器及分配 PROGRAMMABLE CLOCK GENERATOR RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel
ISPPACCLK5520V-01T100I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:In-System Programmable Clock Generator with Universal Fan-Out Buffer
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