參數(shù)資料
型號(hào): ISP1562
廠商: NXP Semiconductors N.V.
英文描述: Hi-Speed Universal Serial Bus PCI Host Controller
中文描述: 高速通用串行總線PCI主機(jī)控制器
文件頁數(shù): 77/98頁
文件大?。?/td> 442K
代理商: ISP1562
9397 750 14223
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 14 July 2005
77 of 98
Philips Semiconductors
ISP1562
USB PCI Host Controller
8
PR
Port Reset
: Logic 1 means the port is in reset. Logic 0 means the port is
not in reset. Default = 0. When software sets this bit from logic 0, the bus
reset sequence as defined in Universal Serial Bus Specification Rev. 2.0is
started. Software clears this bit to terminate the bus reset sequence.
Software must hold this bit at logic 1 until the reset sequence, as specified
in Universal Serial Bus Specification Rev. 2.0 is completed.
Remark:
When software sets this bit, it must also clear the Port Enable bit.
Remark:
When software clears this bit, there may be a delay before the bit
status changes to logic 0 because it will not read logic 0 until the reset is
completed. If the port is in high-speed mode after reset is completed, the
Host Controller will automatically enable this port; it can set the Port Enable
bit. A Host Controller must terminate the reset and stabilize the state of the
port within 2 ms of software changing this bit from logic 1 to logic 0. For
example, if the port detects that the attached device is high-speed during a
reset, then the Host Controller must enable the port within 2 ms of software
clearing this bit.
HCH (bit 12) in the USBSTS register must be logic 0 before software
attempts to use this bit. The Host Controller may hold Port Reset asserted
when the HCH bit is set.
[1]
Suspend
: Default = 0. Logic 1 means the port is in the suspend state.
Logic 0 means the port is not suspended. The PED (Port Enabled) bit and
this bit define the port states as follows:
PED = 0 and SUSP = X —
Port is disabled
PED = 1 and SUSP = 0 —
Port is enabled
PED = 1 and SUSP = 1 —
Port is suspended.
When in the suspend state, downstream propagation of data is blocked on
this port, except for the port reset. If a transaction was in progress when this
bit was set, blocking occurs at the end of the current transaction. In the
suspend state, the port is sensitive to resume detection. The bit status does
not change until the port is suspended and there may be a delay in
suspending a port, if there is a transaction currently in progress on the USB.
Attempts to clear this bit are ignored by the Host Controller. The Host
Controller will unconditionally set this bit to logic 0 when:
Software changes the FPR (Force Port Resume) bit to logic 0.
Software changes the PR (Port Reset) bit to logic 1.
If the host software sets this bit when the Port Enabled bit is logic 0, the
results are undefined.
[1]
7
SUSP
Table 107: PORTSC 1, 2 - Port Status and Control 1, 2 register bit description
…continued
Address: Value read from func2 of address 10h + 64h + (4 x Port Number
1) where Port Number
is 1, 2
Bit
Symbol
Description
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