參數(shù)資料
型號: ISP1562
廠商: NXP Semiconductors N.V.
英文描述: Hi-Speed Universal Serial Bus PCI Host Controller
中文描述: 高速通用串行總線PCI主機(jī)控制器
文件頁數(shù): 20/98頁
文件大?。?/td> 442K
代理商: ISP1562
9397 750 14223
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 14 July 2005
20 of 98
Philips Semiconductors
ISP1562
USB PCI Host Controller
8.2.1.8
Latency Timer register
This register specifies—in units of PCI bus clocks—the value of the Latency Timer for the
PCI bus master.
Table 14
shows the bit description of the Latency Timer register.
8.2.1.9
Header Type register
The Header Type register identifies the layout of the second part of the predefined header,
beginning at byte 10h in configuration space. It also identifies whether the device contains
multiple functions. For bit allocation, see
Table 15
.
8.2.1.10
Base Address register 0
Power-up software must build a consistent address map before booting the machine to an
operating system. This means it must determine how much memory is in the system, and
how much address space the I/O controllers in the system require. After determining this
information, power-up software can map the I/O controllers into reasonable locations and
proceed with system boot. To do this mapping in a device-independent manner, the base
registers for this mapping are placed in the predefined header portion of configuration
space.
Bit 0 in all Base Address registers is read-only and used to determine whether the register
maps into memory or I/O space. Base Address registers that map to memory space must
return logic 0 in bit 0. Base Address registers that map to I/O space must return logic 1 in
bit 0.
The bit description of the BAR 0 register is given in
Table 17
.
Table 13:
Legend: * reset value
Bit
Symbol
7 to 0
CLS[7:0]
CLS - CacheLine Size register (address 0Ch) bit description
Access
R/W
Value
00h*
Description
CacheLine Size
: This byte identifies the system
CacheLine size.
Table 14:
Legend: * reset value
Bit
Symbol
7 to 0
LT[7:0]
LT - Latency Timer register (address 0Dh) bit description
Access
R/W
Value
00h*
Description
Latency Timer
: This byte identifies the latency timer.
Table 15:
Bit
Symbol
Reset
Access
Header Type register (address 0Eh) bit allocation
7
6
MFD
1
0
R
R
5
4
3
2
1
0
HT[6:0]
0
R
0
R
0
R
0
R
0
R
0
R
Table 16:
Bit
7
Header Type register (address 0Eh) bit description
Symbol
Description
MFD
Multi-Function Device
: This bit identifies a multifunction device.
0 —
The device has single function.
1 —
The device has multiple functions.
HT[6:0]
Header Type
: These bits identify the layout of the part of the
predefined header, beginning at byte 10h in configuration space.
6 to 0
相關(guān)PDF資料
PDF描述
ISP1562BE Hi-Speed Universal Serial Bus PCI Host Controller
ISP1581 Universal Serial Bus 2.0 high-speed interface device
ISP1581BD Universal Serial Bus 2.0 high-speed interface device
ISP1582 Hi-Speed Universal Serial Bus peripheral controller
ISP1582BS Hi-Speed Universal Serial Bus peripheral controller
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