參數(shù)資料
型號: ISP1562
廠商: NXP Semiconductors N.V.
英文描述: Hi-Speed Universal Serial Bus PCI Host Controller
中文描述: 高速通用串行總線PCI主機控制器
文件頁數(shù): 59/98頁
文件大?。?/td> 442K
代理商: ISP1562
9397 750 14223
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 14 July 2005
59 of 98
Philips Semiconductors
ISP1562
USB PCI Host Controller
Table 85:
HcRhPortStatus[4:1] - Host Controller Root Hub Port Status[4:1] register bit
description
Address: Value read from func0 or func1 of address 10h + 54h
Bit
Symbol
Description
31 to 21 reserved
-
20
PRSC
PortResetStatusChange
: This bit is set at the end of the 10 ms port reset
signal. The HCD can write logic 1 to clear this bit. Writing logic 0 has no
effect.
0 —
Port reset is not complete
1 —
Port reset is complete.
19
OCIC
PortOverCurrentIndicatorChange
: This bit is valid only if overcurrent
conditions are reported on a per-port basis. This bit is set when the Root
Hub changes the POCI (PortOverCurrentIndicator) bit. The HCD can write
logic 1 to clear this bit. Writing logic 0 has no effect.
0 —
No change in POCI
1 —
POCI has changed.
18
PSSC
PortSuspendStatusChange
: This bit is set when the resume sequence is
completed. This sequence includes the 20 ms resume pulse, LS EOP and
3 ms resynchronization delay. The HCD can write logic 1 to clear this bit.
Writing logic 0 has no effect. This bit is also cleared when
ResetStatusChange is set.
0 —
Resume is not completed
1 —
Resume is completed.
17
PESC
PortEnableStatusChange
: This bit is set when hardware events cause the
PES (PortEnableStatus) bit to be cleared. Changes from the HCD writes do
not set this bit. The HCD can write logic 1 to clear this bit. Writing logic 0
has no effect.
0 —
No change in PES
1 —
Change in PES.
16
CSC
ConnectStatusChange
: This bit is set whenever a connect or disconnect
event occurs. The HCD can write logic 1 to clear this bit. Writing logic 0 has
no effect. If CCS (Current Connect Status) is cleared when a SetPortReset,
SetPortEnable or SetPortSuspend write occurs, this bit is set to force the
driver to re-evaluate the connection status because these writes should not
occur if the port is disconnected.
0 —
No change in CCS
1 —
Change in CCS.
Remark:
If the DeviceRemovable[NDP] bit is set, this bit is set only after a
Root Hub reset to inform the system that the device is attached.
15 to 10 reserved
-
9
LSDA
On read—
LowSpeedDeviceAttached
: This bit indicates the speed of the
device attached to this port. When set, a low-speed device is attached to
this port. When cleared, a full-speed device is attached to this port. This
field is valid only when CCS is set.
0 —
Port is not suspended
1 —
Port is suspended.
On write—
ClearPortPower
: The HCD can clear the PPS
(PortPowerStatus) bit by writing logic 1 to this bit. Writing logic 0 has no
effect.
相關(guān)PDF資料
PDF描述
ISP1562BE Hi-Speed Universal Serial Bus PCI Host Controller
ISP1581 Universal Serial Bus 2.0 high-speed interface device
ISP1581BD Universal Serial Bus 2.0 high-speed interface device
ISP1582 Hi-Speed Universal Serial Bus peripheral controller
ISP1582BS Hi-Speed Universal Serial Bus peripheral controller
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