參數(shù)資料
型號: ISP1181BBS
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Full-speed Universal Serial Bus peripheral controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQCC48
封裝: 7 X 7 MM, 0.85 MM HEIGHT, PLASTIC, MO-220, SOT-619-2, HVQFN-48
文件頁數(shù): 39/70頁
文件大?。?/td> 341K
代理商: ISP1181BBS
Philips Semiconductors
ISP1181B
Full-speed USB peripheral controller
Product data
Rev. 02 — 07 December 2004
39 of 70
9397 750 13958
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Code (Hex): B4 —
read frame number
Transaction —
read 1 or 2 bytes
[1]
Reset value undefined after a bus reset.
12.3.5
Read Chip ID
This command reads the chip identification code and hardware version number. The
firmware must check this information to determine the supported functions and
features. This command accesses the Chip ID Register, which is shown in
Table 46
.
Code (Hex): B5 —
read chip ID
Transaction —
read 2 bytes
Table 42:
Bit
Symbol
Reset
[1]
Access
Bit
Symbol
Reset
[1]
Access
Frame Number Register: bit allocation
15
14
13
12
11
10
9
8
reserved
0
R
5
SOFRH[2:0]
0
R
1
0
R
7
0
R
6
0
R
4
0
R
3
0
R
2
0
R
0
SOFRL[7:0]
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
Table 43:
Bit
15 to 11
10 to 8
7 to 0
Frame Number Register: bit description
Symbol
Description
-
reserved
SOFRH[2:0]
SOF frame number (upper byte)
SOFRL[7:0]
SOF frame number (lower byte)
Table 44:
A0
1
0
0
Example of Frame Number Register access (8-bit bus width)
Phase
Bus lines
Byte #
command
D[7:0]
-
data
D[7:0]
0
data
D[7:0]
1
Description
command code (B4H)
frame number (lower byte)
frame number (upper byte)
Table 45:
A0
1
Example of Frame Number Register access (16-bit bus width)
Phase
Bus lines
Word #
command
D[7:0]
-
D[15:8]
-
data
D[15:0]
0
Description
command code (B4H)
ignored
frame number
0
Table 46:
Bit
Symbol
Reset
Access
Chip ID Register: bit allocation
15
14
13
12
11
10
9
8
CHIPIDH[7:0]
81H
R
R
R
R
R
R
R
R
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